def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.s = Axi4Lite()
self.toMi32 = Axi4Lite_to_Mi32()
self.toAxi = Mi32_to_Axi4Lite()
self.m = Axi4Lite()._m()
def _declr(self):
self.headers = AxiStream()
self.patternMatch = AxiStream()
self.din = AxiStream()
self.dout = AxiStream()._m()
self.cfg = Axi4Lite()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.din = AxiStream()
self.export = AxiStream()._m()
self.cfg = Axi4Lite()
self.hfe = HeadFieldExtractor()
self.patternMatch = PatternMatch()
self.filter = Filter()
self.exporter = Exporter()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.axis_out = AxiStream()._m()
with self._paramsShared(prefix="CNTRL_"):
self.cntrl = Axi4Lite()
reg_t = Bits(self.CNTRL_DATA_WIDTH)
self.conv = AxiLiteEndpoint(
HStruct((reg_t, "enable"), (reg_t, "len")))
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.axi = Axi4Lite()
with self._paramsShared():
# this structure is configuration of interfaces
# fields can also be arrays and metaclass can be used
# to specify field interface and R/W access to field
self.conv = AxiLiteEndpoint(
HStruct((uint32_t, "reg0"), (uint32_t, "reg1")))
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.bus = Axi4Lite()
self.regCntrlLoop0 = Loop(RegCntrl)
self.regCntrlOut0 = RegCntrl()._m()
self.regCntrlLoop1 = Loop(RegCntrl)
self.regCntrlOut1 = RegCntrl()._m()
self.regCntrlLoop2 = Loop(RegCntrl)
self.regCntrlOut2 = RegCntrl()._m()
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.axi = Axi4()._m()
self.dataIn = Handshaked()
cntrl = self.cntrlBus = Axi4Lite()
regs = self.regsConventor = AxiLiteEndpoint(self.REGISTER_MAP)
cntrl._replaceParam(cntrl.ADDR_WIDTH, self.CNTRL_AW)
cntrl._replaceParam(cntrl.DATA_WIDTH, self.DATA_WIDTH)
regs.ADDR_WIDTH.set(self.CNTRL_AW)
regs.DATA_WIDTH.set(self.DATA_WIDTH)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.axi = Axi4()._m()
self.axi.HAS_R = False
self.dataIn = Handshaked()
cntrl = self.cntrlBus = Axi4Lite()
regs = self.regsConventor = AxiLiteEndpoint(self.REGISTER_MAP)
cntrl.ADDR_WIDTH = self.CNTRL_AW
cntrl.DATA_WIDTH = self.DATA_WIDTH
regs.ADDR_WIDTH = self.CNTRL_AW
regs.DATA_WIDTH = self.DATA_WIDTH
def _declr(self):
assert self.CNTRL_ADDR_WIDTH >= self.CNTR_WIDTH
addClkRstn(self)
with self._paramsShared():
self.master = self._axiCls()._m()
self.slave = self._axiCls()
self.cntrl = Axi4Lite()
mem_space = HStruct((Bits(1), "control"), (Bits(32 - 1), None),
(Bits(32), "ar"), (Bits(32), "aw"),
(Bits(32), "r"), (Bits(32), "w"), (Bits(32), "b"))
ep = self.axi_ep = AxiLiteEndpoint(mem_space)
ep.ADDR_WIDTH.set(self.CNTRL_ADDR_WIDTH)
ep.DATA_WIDTH.set(self.CNTRL_DATA_WIDTH)
self.cntrl.ADDR_WIDTH.set(self.CNTRL_ADDR_WIDTH)
self.cntrl.DATA_WIDTH.set(self.CNTRL_DATA_WIDTH)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.s = Axi4Lite()
self.din0 = Handshaked()
self.dout0 = Handshaked()._m()
self.reg = HandshakedReg(Handshaked)
self.din1 = Handshaked()
self.dout1 = Handshaked()._m()
self.other_clk = Clk()
self.other_clk.FREQ = self.clk.FREQ * 2
with self._associated(clk=self.other_clk):
self.other_rst_n = Rst_n()
self.din2 = Handshaked()
self.dout2 = Handshaked()._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.bus = Axi4Lite()
self.signalLoop = SigLoop()
self.signalIn = VectSignal(self.DATA_WIDTH)
self.regCntrlLoop = Loop(RegCntrl)
self.regCntrlOut = RegCntrl()._m()
self.vldSyncedLoop = Loop(VldSynced)
self.vldSyncedOut = VldSynced()._m()
with self._paramsShared(exclude=({"ADDR_WIDTH"}, set())):
self.bramLoop = Loop(BramPort_withoutClk)
self.bramLoop.ADDR_WIDTH = 2
self.bramOut = BramPort_withoutClk()._m()
self.bramOut.ADDR_WIDTH = 2
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.s = self.intfCLs()
self.m = Axi4Lite()._m()
# *_req_fifo are used to aviod blocking during addr/data/confirmation waiting on axi channels
r_f = self.r_req_fifo = HandshakedFifo(HandshakedIdAndLen)
w_f = self.w_req_fifo = HandshakedFifo(HandshakedIdAndLen)
for f in [w_f, r_f]:
f.ID_WIDTH = self.ID_WIDTH
f.LEN_WIDTH = self.intfCLs.LEN_WIDTH
f.DEPTH = self.MAX_TRANS_OVERLAP
with self._paramsShared():
self.out_reg = AxiBuff(Axi4Lite)
self.in_reg = AxiBuff(self.intfCLs)
self.in_reg.DATA_BUFF_DEPTH =\
self.in_reg.ADDR_BUFF_DEPTH = \
self.out_reg.DATA_BUFF_DEPTH = \
self.out_reg.ADDR_BUFF_DEPTH = 1
def _config(self):
self.SIZE = 3
Axi4Lite._config(self)
def _declr(self) -> None:
addClkRstn(self)
with self._paramsShared():
self.s = Axi4Lite()
self.m = Mi32()._m()
def _config(self):
Axi4Lite._config(self)
self.ID_WIDTH = Param(6)
self.LOCK_WIDTH = 1
self.ADDR_USER_WIDTH = Param(0)
def _config(self):
Axi4Lite._config(self)
self.ID_WIDTH = Param(6)
self.LOCK_WIDTH = 1
self.ADDR_USER_WIDTH = Param(0)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
S = int(self.SIZE)
self.a = HObjList(Axi4Lite() for _ in range(S))
self.b = HObjList(Axi4Lite() for _ in range(S))._m()
def _config(self):
self.SIZE = hInt(3)
Axi4Lite._config(self)
def _declr(self):
with self._paramsShared():
self.s = Axi4Lite()
self.m = self.intfCls()._m()
def _config(self):
Axi4Lite._config(self)
def _config(self):
self.SIZE = hInt(3)
Axi4Lite._config(self)
