def apply(self,
dtype: HdlType,
field_path: Optional[TypePath] = None) -> Interface:
"""
Run the connversion
"""
if isinstance(dtype, HStream):
assert dtype.element_t == Bits(8), dtype
assert dtype.start_offsets == (0, ), dtype.start_offsets
assert dtype.len_min >= 1, dtype
i = AxiStream()
i.DATA_WIDTH = 8
else:
i = super(HdlType_to_Interface_with_AxiStream,
self).apply(dtype, field_path)
return i
def connect_r(self, s_r: RamHsR, axi: Axi4, r_cntr: RtlSignal,
CNTR_MAX: int, in_axi_t: Union[HStruct, HUnion]):
self.addr_defaults(axi.ar)
# rm id from r channel as it is not currently supported in frame parser
r_tmp = AxiStream()
r_tmp.USE_STRB = False
r_tmp.DATA_WIDTH = axi.r.DATA_WIDTH
self.r_tmp = r_tmp
r_tmp(axi.r, exclude=(
axi.r.id,
axi.r.resp,
))
r_data = AxiSBuilder(self, r_tmp)\
.parse(in_axi_t).data
if self.data_words_in_axi_word <= 1:
self.connect_addr(s_r.addr.data, axi.ar.addr)
s_r.data.data(r_data.data[s_r.DATA_WIDTH:])
ar_sn = StreamNode([s_r.addr], [axi.ar])
r_sn = StreamNode([r_data], [s_r.data])
else:
addr, sub_addr = self.split_subaddr(s_r.addr.data)
self.connect_addr(addr, axi.ar.addr)
sel = HsBuilder(self, r_data._select, master_to_slave=False)\
.buff(self.MAX_TRANS_OVERLAP).end
sel.data(sub_addr)
data_items = [
getattr(r_data, f"data{i:d}").data
for i in range(self.data_words_in_axi_word)
]
r_data_selected = HsBuilder.join_prioritized(self, data_items).end
s_r.data.data(r_data_selected.data)
ar_sn = StreamNode([s_r.addr], [axi.ar, sel])
r_sn = StreamNode([r_data_selected], [s_r.data])
ar_sn.sync(r_cntr != CNTR_MAX)
r_sn.sync()
r_en = r_sn.ack()
If(axi.ar.ready & axi.ar.valid,
If(~r_en, r_cntr(r_cntr + 1))).Elif(r_en, r_cntr(r_cntr - 1))