# ar fsm next
If(arRd,
# rdIdle
If(arVld,
rSt(rSt_t.rdData)
).Else(
rSt(rSt_t.rdIdle)
)
).Else(
# rdData
If(rRd & rVld,
rSt(rSt_t.rdIdle)
).Else(
rSt(rSt_t.rdData)
)
)
r_idle(rSt._eq(rSt_t.rdIdle))
return n, {
r_idle: DIRECTION.OUT,
arRd: DIRECTION.IN,
arVld: DIRECTION.IN,
rVld: DIRECTION.IN,
rRd: DIRECTION.IN
}
if __name__ == "__main__":
netlist, interfaces = AxiReaderCore()
print(netlistToVhdlStr("AxiReaderCore", netlist, interfaces))
SIGNAL counter_next: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
assig_process_counter: PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
counter <= X"00";
ELSE
counter <= counter_next;
END IF;
END IF;
END PROCESS;
assig_process_counter_next: PROCESS (counter, en, start)
BEGIN
IF start = '1' THEN
counter_next <= boundary;
ELSIF en = '1' THEN
counter_next <= STD_LOGIC_VECTOR(UNSIGNED(counter) - 1);
ELSE
counter_next <= counter;
END IF;
END PROCESS;
s_out <= counter;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = SimpleWhile()
print(netlistToVhdlStr("SimpleWhile", netlist, interfaces))
ARCHITECTURE rtl OF SwitchStatement IS
BEGIN
assig_process_output: PROCESS (input)
BEGIN
CASE input IS
WHEN X"00" =>
output <= X"01";
WHEN X"01" =>
output <= X"02";
WHEN X"02" =>
output <= X"03";
WHEN X"03" =>
output <= X"04";
WHEN X"04" =>
output <= X"05";
WHEN X"05" =>
output <= X"06";
WHEN X"06" =>
output <= X"07";
WHEN X"07" =>
output <= X"08";
END CASE;
END PROCESS;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = SwitchStatement()
print(netlistToVhdlStr("SwitchStatement", netlist, interfaces))
PORT (arRd: IN STD_LOGIC;
arVld: IN STD_LOGIC;
rRd: IN STD_LOGIC;
rSt: OUT rSt_t;
rVld: IN STD_LOGIC
);
END AxiReaderCore;
ARCHITECTURE rtl OF AxiReaderCore IS
BEGIN
assig_process_rSt: PROCESS (arRd, arVld, rRd, rVld)
BEGIN
IF arRd = '1' THEN
IF arVld = '1' THEN
rSt <= rdData;
ELSE
rSt <= rdIdle;
END IF;
ELSIF (rRd AND rVld) = '1' THEN
rSt <= rdIdle;
ELSE
rSt <= rdData;
END IF;
END PROCESS;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = AxiReaderCore()
print(netlistToVhdlStr("AxiReaderCore", netlist, interfaces))
END LeadingZero;
ARCHITECTURE rtl OF LeadingZero IS
BEGIN
assig_process_s_indexOfFirstZero: PROCESS (s_in)
BEGIN
IF (s_in(0)) = '0' THEN
s_indexOfFirstZero <= X"00";
ELSIF (s_in(1)) = '0' THEN
s_indexOfFirstZero <= X"01";
ELSIF (s_in(2)) = '0' THEN
s_indexOfFirstZero <= X"02";
ELSIF (s_in(3)) = '0' THEN
s_indexOfFirstZero <= X"03";
ELSIF (s_in(4)) = '0' THEN
s_indexOfFirstZero <= X"04";
ELSIF (s_in(5)) = '0' THEN
s_indexOfFirstZero <= X"05";
ELSIF (s_in(6)) = '0' THEN
s_indexOfFirstZero <= X"06";
ELSE
s_indexOfFirstZero <= X"07";
END IF;
END PROCESS;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = LeadingZero()
print(netlistToVhdlStr("LeadingZero", netlist, interfaces))
tsWaitLogic(st(st))
).Case(stT.ts0Wait,
If(sd0,
st(stT.lenExtr)
)
).Case(stT.ts1Wait,
If(sd1,
st(stT.lenExtr)
)
).Case(stT.lenExtr,
If(cntrlFifoVld & cntrlFifoLast,
st(stT.idle)
)
)
s_idle(st._eq(stT.idle))
return n, {
rst: DIRECTION.IN,
clk: DIRECTION.IN,
sd0: DIRECTION.IN,
sd1: DIRECTION.IN,
cntrlFifoVld: DIRECTION.IN,
cntrlFifoLast: DIRECTION.IN,
s_idle: DIRECTION.OUT
}
if __name__ == "__main__":
netlist, interfaces = ComplexConditions()
print(netlistToVhdlStr("ComplexConditions", netlist, interfaces))
def test_indexOps(self):
c, interf = IndexOps()
s = netlistToVhdlStr("IndexOps", c, interf)
self.assertNotIn("sig_", s)
END LeadingZero;
ARCHITECTURE rtl OF LeadingZero IS
BEGIN
assig_process_s_indexOfFirstZero: PROCESS (s_in)
BEGIN
IF (s_in(0)) = '0' THEN
s_indexOfFirstZero <= X"00";
ELSIF (s_in(1)) = '0' THEN
s_indexOfFirstZero <= X"01";
ELSIF (s_in(2)) = '0' THEN
s_indexOfFirstZero <= X"02";
ELSIF (s_in(3)) = '0' THEN
s_indexOfFirstZero <= X"03";
ELSIF (s_in(4)) = '0' THEN
s_indexOfFirstZero <= X"04";
ELSIF (s_in(5)) = '0' THEN
s_indexOfFirstZero <= X"05";
ELSIF (s_in(6)) = '0' THEN
s_indexOfFirstZero <= X"06";
ELSE
s_indexOfFirstZero <= X"07";
END IF;
END PROCESS;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = LeadingZero()
print(netlistToVhdlStr("LeadingZero", netlist, interfaces))
from hwtLib.examples.rtlLvl.netlistToRtl import netlistToVhdlStr
from ipCorePackager.constants import DIRECTION
def SimpleRegister():
t = Bits(8)
n = RtlNetlist()
s_out = n.sig("s_out", t)
s_in = n.sig("s_in", t)
clk = n.sig("clk")
syncRst = n.sig("rst")
val = n.sig("val", t, clk, syncRst, 0)
val(s_in)
s_out(val)
interf = {
clk: DIRECTION.IN,
syncRst: DIRECTION.IN,
s_in: DIRECTION.IN,
s_out: DIRECTION.OUT
}
return n, interf
if __name__ == "__main__":
netlist, interfaces = SimpleRegister()
print(netlistToVhdlStr("SimpleRegister", netlist, interfaces))
SIGNAL counter_next: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
assig_process_counter: PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
counter <= X"00";
ELSE
counter <= counter_next;
END IF;
END IF;
END PROCESS;
assig_process_counter_next: PROCESS (counter, en, start)
BEGIN
IF start = '1' THEN
counter_next <= boundary;
ELSIF en = '1' THEN
counter_next <= STD_LOGIC_VECTOR(UNSIGNED(counter) - 1);
ELSE
counter_next <= counter;
END IF;
END PROCESS;
s_out <= counter;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = SimpleWhile()
print(netlistToVhdlStr("SimpleWhile", netlist, interfaces))
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
from hwt.code import Switch
from hwt.hdl.types.bits import Bits
from hwt.synthesizer.rtlLevel.netlist import RtlNetlist
from hwtLib.examples.rtlLvl.netlistToRtl import netlistToVhdlStr
from ipCorePackager.constants import DIRECTION
def SwitchStatement():
t = Bits(8)
n = RtlNetlist()
In = n.sig("input", t, def_val=8)
Out = n.sig("output", t)
Switch(In).add_cases([(i, Out(i + 1)) for i in range(8)])
interf = {In: DIRECTION.IN, Out: DIRECTION.OUT}
return n, interf
if __name__ == "__main__":
netlist, interfaces = SwitchStatement()
print(netlistToVhdlStr("SwitchStatement", netlist, interfaces))
st_next <= ts0Wait;
ELSE
st_next <= st;
END IF;
WHEN ts0Wait =>
IF sd0 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN ts1Wait =>
IF sd1 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (ctrlFifoVld AND ctrlFifoLast) = '1' THEN
st_next <= idle;
ELSE
st_next <= st;
END IF;
END CASE;
END PROCESS;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = ComplexConditions()
print(netlistToVhdlStr("ComplexConditions", netlist, interfaces))
ARCHITECTURE rtl OF Counter IS
SIGNAL cnt: STD_LOGIC_VECTOR(7 DOWNTO 0) := X"00";
SIGNAL cnt_next: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
assig_process_cnt: PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
cnt <= X"00";
ELSE
cnt <= cnt_next;
END IF;
END IF;
END PROCESS;
assig_process_cnt_next: PROCESS (cnt, en)
BEGIN
IF en = '1' THEN
cnt_next <= STD_LOGIC_VECTOR(UNSIGNED(cnt) + 1);
ELSE
cnt_next <= cnt;
END IF;
END PROCESS;
s_out <= cnt;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = Counter()
print(netlistToVhdlStr("Counter", netlist, interfaces))
def cmp(self, getNetlistFn, file_name):
netlist, interfaces = getNetlistFn()
vhdl = netlistToVhdlStr(getNetlistFn.__name__, netlist, interfaces)
self.assert_same_as_file(vhdl, file_name)
SIGNAL fsmSt_next: fsmT;
BEGIN
assig_process_fsmSt: PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
fsmSt <= send0;
ELSE
fsmSt <= fsmSt_next;
END IF;
END IF;
END PROCESS;
assig_process_fsmSt_next: PROCESS (fsmSt, s_in0, s_in1)
BEGIN
IF fsmSt = send0 THEN
s_out <= s_in0;
fsmSt_next <= send1;
ELSE
s_out <= s_in1;
fsmSt_next <= send0;
END IF;
END PROCESS;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = SimpleEnum()
print(netlistToVhdlStr("SimpleEnum", netlist, interfaces))
s_out4 = n.sig("s_out4", Bits(16))
s_out(s_in[4:]._concat(Bits(4).from_py(2)))
s_out2[4:](s_in2[4:])
s_out2[:4](s_in2[:4])
s_out3(s_in3[8:])
s_out4[8:](s_in4a)
s_out4[(8 + 8):8](s_in4b)
interf = {
s_in: DIRECTION.IN,
s_out: DIRECTION.OUT,
s_in2: DIRECTION.IN,
s_out2: DIRECTION.OUT,
s_in3: DIRECTION.IN,
s_out3: DIRECTION.OUT,
s_in4a: DIRECTION.IN,
s_in4b: DIRECTION.IN,
s_out4: DIRECTION.OUT
}
return n, interf
if __name__ == "__main__":
netlist, interfaces = IndexOps()
print(netlistToVhdlStr("IndexOps", netlist, interfaces))
def cmp(self, getNetlistFn, expected):
netlist, interfaces = getNetlistFn()
self.strStructureCmp(
netlistToVhdlStr(getNetlistFn.__name__, netlist, interfaces),
expected)
ARCHITECTURE rtl OF Counter IS
SIGNAL cnt: STD_LOGIC_VECTOR(7 DOWNTO 0) := X"00";
SIGNAL cnt_next: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
assig_process_cnt: PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
cnt <= X"00";
ELSE
cnt <= cnt_next;
END IF;
END IF;
END PROCESS;
assig_process_cnt_next: PROCESS (cnt, en)
BEGIN
IF en = '1' THEN
cnt_next <= STD_LOGIC_VECTOR(UNSIGNED(cnt) + 1);
ELSE
cnt_next <= cnt;
END IF;
END PROCESS;
s_out <= cnt;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = Counter()
print(netlistToVhdlStr("Counter", netlist, interfaces))
def cmp(self, getNetlistFn, expected):
netlist, interfaces = getNetlistFn()
self.strStructureCmp(netlistToVhdlStr(
getNetlistFn.__name__, netlist, interfaces), expected)
indexOpsExpected = """library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY IndexOps IS
PORT (s_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_in2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_in3: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_in4a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_in4b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out2: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out3: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out4: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END IndexOps;
ARCHITECTURE rtl OF IndexOps IS
BEGIN
s_out <= (s_in(3 DOWNTO 0)) & X"2";
s_out2(3 DOWNTO 0) <= s_in2(3 DOWNTO 0);
s_out2(7 DOWNTO 4) <= s_in2(7 DOWNTO 4);
s_out3 <= s_in3(7 DOWNTO 0);
s_out4(7 DOWNTO 0) <= s_in4a;
s_out4(15 DOWNTO 8) <= s_in4b;
END ARCHITECTURE rtl;"""
if __name__ == "__main__":
netlist, interfaces = IndexOps()
print(netlistToVhdlStr("IndexOps", netlist, interfaces))
