def bench(): # Parameters TARGET = "SIM" # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) btnu = Signal(bool(0)) btnl = Signal(bool(0)) btnd = Signal(bool(0)) btnr = Signal(bool(0)) btnc = Signal(bool(0)) sw = Signal(intbv(0)[4:]) i2c_scl_i = Signal(bool(1)) i2c_sda_i = Signal(bool(1)) phy_gmii_clk = Signal(bool(0)) phy_gmii_rst = Signal(bool(0)) phy_gmii_clk_en = Signal(bool(0)) phy_gmii_rxd = Signal(intbv(0)[8:]) phy_gmii_rx_dv = Signal(bool(0)) phy_gmii_rx_er = Signal(bool(0)) phy_int_n = Signal(bool(1)) uart_rxd = Signal(bool(1)) uart_cts = Signal(bool(1)) s1_scl_i = Signal(bool(1)) s1_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs led = Signal(intbv(0)[8:]) i2c_scl_o = Signal(bool(1)) i2c_scl_t = Signal(bool(1)) i2c_sda_o = Signal(bool(1)) i2c_sda_t = Signal(bool(1)) phy_gmii_txd = Signal(intbv(0)[8:]) phy_gmii_tx_en = Signal(bool(0)) phy_gmii_tx_er = Signal(bool(0)) phy_reset_n = Signal(bool(0)) uart_txd = Signal(bool(1)) uart_rts = Signal(bool(1)) s1_scl_o = Signal(bool(1)) s1_scl_t = Signal(bool(1)) s1_sda_o = Signal(bool(1)) s1_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # sources and sinks gmii_source = gmii_ep.GMIISource() gmii_source_logic = gmii_source.create_logic(phy_gmii_clk, phy_gmii_rst, txd=phy_gmii_rxd, tx_en=phy_gmii_rx_dv, tx_er=phy_gmii_rx_er, clk_enable=phy_gmii_clk_en, name='gmii_source') gmii_sink = gmii_ep.GMIISink() gmii_sink_logic = gmii_sink.create_logic(phy_gmii_clk, phy_gmii_rst, rxd=phy_gmii_txd, rx_dv=phy_gmii_tx_en, rx_er=phy_gmii_tx_er, clk_enable=phy_gmii_clk_en, name='gmii_sink') uart_source = uart_ep.UARTSource() uart_source_logic = uart_source.create_logic(clk, rst, txd=uart_rxd, prescale=int(125000000 / (115200 * 8)), name='uart_source') uart_sink = uart_ep.UARTSink() uart_sink_logic = uart_sink.create_logic(clk, rst, rxd=uart_txd, prescale=int(125000000 / (115200 * 8)), name='uart_sink') # I2C memory model 1 i2c_mem1 = i2c.I2CMem(1024) i2c_mem_logic1 = i2c_mem1.create_logic(scl_i=s1_scl_i, scl_o=s1_scl_o, scl_t=s1_scl_t, sda_i=s1_sda_i, sda_o=s1_sda_o, sda_t=s1_sda_t, abw=2, address=0x50, latency=0, name='slave1') # I2C memory model 2 i2c_mem2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem2.create_logic(scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=1000, name='slave2') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, btnu=btnu, btnl=btnl, btnd=btnd, btnr=btnr, btnc=btnc, sw=sw, led=led, i2c_scl_i=i2c_scl_i, i2c_scl_o=i2c_scl_o, i2c_scl_t=i2c_scl_t, i2c_sda_i=i2c_sda_i, i2c_sda_o=i2c_sda_o, i2c_sda_t=i2c_sda_t, phy_gmii_clk=phy_gmii_clk, phy_gmii_rst=phy_gmii_rst, phy_gmii_clk_en=phy_gmii_clk_en, phy_gmii_rxd=phy_gmii_rxd, phy_gmii_rx_dv=phy_gmii_rx_dv, phy_gmii_rx_er=phy_gmii_rx_er, phy_gmii_txd=phy_gmii_txd, phy_gmii_tx_en=phy_gmii_tx_en, phy_gmii_tx_er=phy_gmii_tx_er, phy_reset_n=phy_reset_n, phy_int_n=phy_int_n, uart_rxd=uart_rxd, uart_txd=uart_txd, uart_rts=uart_rts, uart_cts=uart_cts) @always_comb def bus(): # emulate I2C wired AND i2c_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o i2c_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o s1_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o s1_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o s2_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o s2_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o @always(delay(4)) def clkgen(): clk.next = not clk phy_gmii_clk.next = not phy_gmii_clk clk_enable_rate = Signal(int(0)) clk_enable_div = Signal(int(0)) @always(clk.posedge) def clk_enable_gen(): if clk_enable_div.next > 0: phy_gmii_clk_en.next = 0 clk_enable_div.next = clk_enable_div - 1 else: phy_gmii_clk_en.next = 1 clk_enable_div.next = clk_enable_rate - 1 @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 phy_gmii_rst.next = 1 yield clk.posedge rst.next = 0 phy_gmii_rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: enumerate via UDP") current_test.next = 1 pkt = xfcp.XFCPFrame() pkt.path = [] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' test_frame = udp_ep.UDPFrame() test_frame.eth_dest_mac = 0x020000000000 test_frame.eth_src_mac = 0xDAD1D2D3D4D5 test_frame.eth_type = 0x0800 test_frame.ip_version = 4 test_frame.ip_ihl = 5 test_frame.ip_dscp = 0 test_frame.ip_ecn = 0 test_frame.ip_length = None test_frame.ip_identification = 0 test_frame.ip_flags = 2 test_frame.ip_fragment_offset = 0 test_frame.ip_ttl = 64 test_frame.ip_protocol = 0x11 test_frame.ip_header_checksum = None test_frame.ip_source_ip = 0xc0a80181 test_frame.ip_dest_ip = 0xc0a80180 test_frame.udp_source_port = 1234 test_frame.udp_dest_port = 14000 test_frame.payload = pkt.build_axis() test_frame.build() gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame.build_eth().build_axis_fcs().data) # wait for ARP request packet rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = arp_ep.ARPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0806 assert check_frame.arp_htype == 0x0001 assert check_frame.arp_ptype == 0x0800 assert check_frame.arp_hlen == 6 assert check_frame.arp_plen == 4 assert check_frame.arp_oper == 1 assert check_frame.arp_sha == 0x020000000000 assert check_frame.arp_spa == 0xc0a80180 assert check_frame.arp_tha == 0x000000000000 assert check_frame.arp_tpa == 0xc0a80181 # generate response arp_frame = arp_ep.ARPFrame() arp_frame.eth_dest_mac = 0x020000000000 arp_frame.eth_src_mac = 0xDAD1D2D3D4D5 arp_frame.eth_type = 0x0806 arp_frame.arp_htype = 0x0001 arp_frame.arp_ptype = 0x0800 arp_frame.arp_hlen = 6 arp_frame.arp_plen = 4 arp_frame.arp_oper = 2 arp_frame.arp_sha = 0xDAD1D2D3D4D5 arp_frame.arp_spa = 0xc0a80181 arp_frame.arp_tha = 0x020000000000 arp_frame.arp_tpa = 0xc0a80180 gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + arp_frame.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5 assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0800 assert check_frame.ip_version == 4 assert check_frame.ip_ihl == 5 assert check_frame.ip_dscp == 0 assert check_frame.ip_ecn == 0 assert check_frame.ip_identification == 0 assert check_frame.ip_flags == 2 assert check_frame.ip_fragment_offset == 0 assert check_frame.ip_ttl == 64 assert check_frame.ip_protocol == 0x11 assert check_frame.ip_source_ip == 0xc0a80180 assert check_frame.ip_dest_ip == 0xc0a80181 assert check_frame.udp_source_port == 14000 assert check_frame.udp_dest_port == 1234 rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 64 pkt = xfcp.XFCPFrame() pkt.path = [0] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' test_frame = udp_ep.UDPFrame() test_frame.eth_dest_mac = 0x020000000000 test_frame.eth_src_mac = 0xDAD1D2D3D4D5 test_frame.eth_type = 0x0800 test_frame.ip_version = 4 test_frame.ip_ihl = 5 test_frame.ip_dscp = 0 test_frame.ip_ecn = 0 test_frame.ip_length = None test_frame.ip_identification = 0 test_frame.ip_flags = 2 test_frame.ip_fragment_offset = 0 test_frame.ip_ttl = 64 test_frame.ip_protocol = 0x11 test_frame.ip_header_checksum = None test_frame.ip_source_ip = 0xc0a80181 test_frame.ip_dest_ip = 0xc0a80180 test_frame.udp_source_port = 1234 test_frame.udp_dest_port = 14000 test_frame.payload = pkt.build_axis() test_frame.build() gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5 assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0800 assert check_frame.ip_version == 4 assert check_frame.ip_ihl == 5 assert check_frame.ip_dscp == 0 assert check_frame.ip_ecn == 0 assert check_frame.ip_identification == 0 assert check_frame.ip_flags == 2 assert check_frame.ip_fragment_offset == 0 assert check_frame.ip_ttl == 64 assert check_frame.ip_protocol == 0x11 assert check_frame.ip_source_ip == 0xc0a80180 assert check_frame.ip_dest_ip == 0xc0a80181 assert check_frame.udp_source_port == 14000 assert check_frame.udp_dest_port == 1234 rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [0] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 32 assert gmii_source.empty() assert gmii_sink.empty() yield delay(100) yield clk.posedge print("test 1: test write and read RAM 0") current_test.next = 1 pkt1 = xfcp.XFCPFrame() pkt1.path = [0] pkt1.ptype = 0x12 pkt1.payload = bytearray( struct.pack('<BH', 0, 4) + b'\x11\x22\x33\x44') pkt2 = xfcp.XFCPFrame() pkt2.path = [0] pkt2.ptype = 0x10 pkt2.payload = bytearray(struct.pack('<BH', 0, 4)) test_frame1 = udp_ep.UDPFrame() test_frame1.eth_dest_mac = 0x020000000000 test_frame1.eth_src_mac = 0xDAD1D2D3D4D5 test_frame1.eth_type = 0x0800 test_frame1.ip_version = 4 test_frame1.ip_ihl = 5 test_frame1.ip_dscp = 0 test_frame1.ip_ecn = 0 test_frame1.ip_length = None test_frame1.ip_identification = 0 test_frame1.ip_flags = 2 test_frame1.ip_fragment_offset = 0 test_frame1.ip_ttl = 64 test_frame1.ip_protocol = 0x11 test_frame1.ip_header_checksum = None test_frame1.ip_source_ip = 0xc0a80181 test_frame1.ip_dest_ip = 0xc0a80180 test_frame1.udp_source_port = 1234 test_frame1.udp_dest_port = 14000 test_frame1.payload = pkt1.build_axis() test_frame1.build() test_frame2 = udp_ep.UDPFrame(test_frame1) test_frame2.payload = pkt2.build_axis() test_frame2.build() gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1.build_eth().build_axis_fcs().data) gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0x13 assert rx_pkt.payload.data == struct.pack('<BH', 0, 4) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0x11 assert rx_pkt.payload.data == struct.pack('<BH', 0, 4) + b'\x11\x22\x33\x44' assert gmii_source.empty() assert gmii_sink.empty() yield delay(100) yield clk.posedge print("test 3: enumerate via UART") current_test.next = 3 pkt = xfcp.XFCPFrame() pkt.path = [] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' uart_source.write(pkt.build_axis_cobs().data + b'\x00') yield clk.posedge rx_data = b'' while True: if not uart_sink.empty(): b = bytearray(uart_sink.read(1)) rx_data += b if b[0] == 0: break yield clk.posedge rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis_cobs(rx_data[:-1]) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 64 pkt = xfcp.XFCPFrame() pkt.path = [0] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' uart_source.write(pkt.build_axis_cobs().data + b'\x00') yield clk.posedge rx_data = b'' while True: if not uart_sink.empty(): b = bytearray(uart_sink.read(1)) rx_data += b if b[0] == 0: break yield clk.posedge rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis_cobs(rx_data[:-1]) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [0] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 32 yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters DEFAULT_PRESCALE = 1 FIXED_PRESCALE = 0 CMD_FIFO = 1 CMD_FIFO_ADDR_WIDTH = 5 WRITE_FIFO = 1 WRITE_FIFO_ADDR_WIDTH = 5 READ_FIFO = 1 READ_FIFO_ADDR_WIDTH = 5 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) wbs_adr_i = Signal(intbv(0)[3:]) wbs_dat_i = Signal(intbv(0)[16:]) wbs_we_i = Signal(bool(0)) wbs_sel_i = Signal(intbv(0)[2:]) wbs_stb_i = Signal(bool(0)) wbs_cyc_i = Signal(bool(0)) i2c_scl_i = Signal(bool(1)) i2c_sda_i = Signal(bool(1)) s1_scl_i = Signal(bool(1)) s1_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs wbs_dat_o = Signal(intbv(0)[16:]) wbs_ack_o = Signal(bool(0)) i2c_scl_o = Signal(bool(1)) i2c_scl_t = Signal(bool(1)) i2c_sda_o = Signal(bool(1)) i2c_sda_t = Signal(bool(1)) s1_scl_o = Signal(bool(1)) s1_scl_t = Signal(bool(1)) s1_sda_o = Signal(bool(1)) s1_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # WB master wbm_inst = wb.WBMaster() wbm_logic = wbm_inst.create_logic(clk, adr_o=wbs_adr_i, dat_i=wbs_dat_o, dat_o=wbs_dat_i, we_o=wbs_we_i, sel_o=wbs_sel_i, stb_o=wbs_stb_i, ack_i=wbs_ack_o, cyc_o=wbs_cyc_i, name='master') # I2C memory model 1 i2c_mem_inst1 = i2c.I2CMem(1024) i2c_mem_logic1 = i2c_mem_inst1.create_logic(scl_i=s1_scl_i, scl_o=s1_scl_o, scl_t=s1_scl_t, sda_i=s1_sda_i, sda_o=s1_sda_o, sda_t=s1_sda_t, abw=2, address=0x50, latency=0, name='slave1') # I2C memory model 2 i2c_mem_inst2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem_inst2.create_logic(scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=1000, name='slave2') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, wbs_adr_i=wbs_adr_i, wbs_dat_i=wbs_dat_i, wbs_dat_o=wbs_dat_o, wbs_we_i=wbs_we_i, wbs_sel_i=wbs_sel_i, wbs_stb_i=wbs_stb_i, wbs_ack_o=wbs_ack_o, wbs_cyc_i=wbs_cyc_i, i2c_scl_i=i2c_scl_i, i2c_scl_o=i2c_scl_o, i2c_scl_t=i2c_scl_t, i2c_sda_i=i2c_sda_i, i2c_sda_o=i2c_sda_o, i2c_sda_t=i2c_sda_t) @always_comb def bus(): # emulate I2C wired AND i2c_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o i2c_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o s1_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o s1_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o s2_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o s2_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: write") current_test.next = 1 wbm_inst.init_write(2, b'\x50\x04\x00') wbm_inst.init_write(3, b'\x04\x04') wbm_inst.init_write(3, b'\x04\x11') wbm_inst.init_write(3, b'\x04\x22') wbm_inst.init_write(3, b'\x04\x33') wbm_inst.init_write(3, b'\x14\x44') yield wbm_inst.wait() yield clk.posedge while True: wbm_inst.init_read(0, 1) yield wbm_inst.wait() data = wbm_inst.get_read_data() if data[1][0] & 0x03 == 0: break data = i2c_mem_inst1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem_inst1.read_mem(4, 4) == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 wbm_inst.init_write(2, b'\x50\x04\x00') wbm_inst.init_write(3, b'\x04\x04') wbm_inst.init_write(3, b'\x03') wbm_inst.init_write(3, b'\x02') wbm_inst.init_write(3, b'\x02') wbm_inst.init_write(3, b'\x12') yield wbm_inst.wait() yield clk.posedge while True: wbm_inst.init_read(0, 1) yield wbm_inst.wait() data = wbm_inst.get_read_data() if data[1][0] & 0x03 == 0: break wbm_inst.init_read(4, 2) wbm_inst.init_read(4, 2) wbm_inst.init_read(4, 2) wbm_inst.init_read(4, 2) yield wbm_inst.wait() yield clk.posedge data = wbm_inst.get_read_data() assert data[1] == b'\x11\x00' data = wbm_inst.get_read_data() assert data[1] == b'\x22\x00' data = wbm_inst.get_read_data() assert data[1] == b'\x33\x00' data = wbm_inst.get_read_data() assert data[1] == b'\x44\x01' yield delay(100) yield clk.posedge print("test 3: write to slave 2") current_test.next = 3 wbm_inst.init_write(2, b'\x51\x08\x00\x00') wbm_inst.init_write(4, b'\x04\x00') wbm_inst.init_write(4, b'\x44\x00') wbm_inst.init_write(4, b'\x33\x00') wbm_inst.init_write(4, b'\x22\x00') wbm_inst.init_write(4, b'\x11\x01') wbm_inst.init_write(3, b'\x10') yield wbm_inst.wait() yield clk.posedge while True: wbm_inst.init_read(0, 1) yield wbm_inst.wait() data = wbm_inst.get_read_data() if data[1][0] & 0x03 == 0: break data = i2c_mem_inst2.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem_inst2.read_mem(4, 4) == b'\x44\x33\x22\x11' yield delay(100) yield clk.posedge print("test 4: read from slave 2") current_test.next = 4 wbm_inst.init_write(2, b'\x51\x04\x00') wbm_inst.init_write(3, b'\x04\x04') wbm_inst.init_write(3, b'\x03') wbm_inst.init_write(3, b'\x02') wbm_inst.init_write(3, b'\x02') wbm_inst.init_write(3, b'\x12') yield wbm_inst.wait() yield clk.posedge while True: wbm_inst.init_read(0, 1) yield wbm_inst.wait() data = wbm_inst.get_read_data() if data[1][0] & 0x03 == 0: break wbm_inst.init_read(4, 2) wbm_inst.init_read(4, 2) wbm_inst.init_read(4, 2) wbm_inst.init_read(4, 2) yield wbm_inst.wait() yield clk.posedge data = wbm_inst.get_read_data() assert data[1] == b'\x44\x00' data = wbm_inst.get_read_data() assert data[1] == b'\x33\x00' data = wbm_inst.get_read_data() assert data[1] == b'\x22\x00' data = wbm_inst.get_read_data() assert data[1] == b'\x11\x01' yield delay(100) yield clk.posedge print("test 5: write to nonexistent device") current_test.next = 5 wbm_inst.init_write(2, b'\x52\x04\x00') wbm_inst.init_write(3, b'\x04\x04') wbm_inst.init_write(3, b'\x04\xde') wbm_inst.init_write(3, b'\x04\xad') wbm_inst.init_write(3, b'\x04\xbe') wbm_inst.init_write(3, b'\x14\xef') yield wbm_inst.wait() yield clk.posedge got_missed_ack = False while True: wbm_inst.init_read(0, 1) yield wbm_inst.wait() data = wbm_inst.get_read_data() if data[1][0] & 0x08: got_missed_ack = True if data[1][0] & 0x03 == 0: break assert got_missed_ack yield delay(100) raise StopSimulation return dut, wbm_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check
def bench(): # Parameters DEFAULT_PRESCALE = 1 FIXED_PRESCALE = 0 CMD_FIFO = 1 CMD_FIFO_ADDR_WIDTH = 5 WRITE_FIFO = 1 WRITE_FIFO_ADDR_WIDTH = 5 READ_FIFO = 1 READ_FIFO_ADDR_WIDTH = 5 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) s_axil_awaddr = Signal(intbv(0)[4:]) s_axil_awprot = Signal(intbv(0)[3:]) s_axil_awvalid = Signal(bool(0)) s_axil_wdata = Signal(intbv(0)[32:]) s_axil_wstrb = Signal(intbv(0)[4:]) s_axil_wvalid = Signal(bool(0)) s_axil_bready = Signal(bool(0)) s_axil_araddr = Signal(intbv(0)[4:]) s_axil_arprot = Signal(intbv(0)[3:]) s_axil_arvalid = Signal(bool(0)) s_axil_rready = Signal(bool(0)) i2c_scl_i = Signal(bool(1)) i2c_sda_i = Signal(bool(1)) s1_scl_i = Signal(bool(1)) s1_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs s_axil_awready = Signal(bool(0)) s_axil_wready = Signal(bool(0)) s_axil_bresp = Signal(intbv(0)[2:]) s_axil_bvalid = Signal(bool(0)) s_axil_arready = Signal(bool(0)) s_axil_rdata = Signal(intbv(0)[32:]) s_axil_rresp = Signal(intbv(0)[2:]) s_axil_rvalid = Signal(bool(0)) i2c_scl_o = Signal(bool(1)) i2c_scl_t = Signal(bool(1)) i2c_sda_o = Signal(bool(1)) i2c_sda_t = Signal(bool(1)) s1_scl_o = Signal(bool(1)) s1_scl_t = Signal(bool(1)) s1_sda_o = Signal(bool(1)) s1_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # AXI4-Lite master axil_master_inst = axil.AXILiteMaster() axil_master_pause = Signal(bool(False)) axil_master_logic = axil_master_inst.create_logic( clk, rst, m_axil_awaddr=s_axil_awaddr, m_axil_awprot=s_axil_awprot, m_axil_awvalid=s_axil_awvalid, m_axil_awready=s_axil_awready, m_axil_wdata=s_axil_wdata, m_axil_wstrb=s_axil_wstrb, m_axil_wvalid=s_axil_wvalid, m_axil_wready=s_axil_wready, m_axil_bresp=s_axil_bresp, m_axil_bvalid=s_axil_bvalid, m_axil_bready=s_axil_bready, m_axil_araddr=s_axil_araddr, m_axil_arprot=s_axil_arprot, m_axil_arvalid=s_axil_arvalid, m_axil_arready=s_axil_arready, m_axil_rdata=s_axil_rdata, m_axil_rresp=s_axil_rresp, m_axil_rvalid=s_axil_rvalid, m_axil_rready=s_axil_rready, pause=axil_master_pause, name='master') # I2C memory model 1 i2c_mem_inst1 = i2c.I2CMem(1024) i2c_mem_logic1 = i2c_mem_inst1.create_logic(scl_i=s1_scl_i, scl_o=s1_scl_o, scl_t=s1_scl_t, sda_i=s1_sda_i, sda_o=s1_sda_o, sda_t=s1_sda_t, abw=2, address=0x50, latency=0, name='slave1') # I2C memory model 2 i2c_mem_inst2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem_inst2.create_logic(scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=1000, name='slave2') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, s_axil_awaddr=s_axil_awaddr, s_axil_awprot=s_axil_awprot, s_axil_awvalid=s_axil_awvalid, s_axil_awready=s_axil_awready, s_axil_wdata=s_axil_wdata, s_axil_wstrb=s_axil_wstrb, s_axil_wvalid=s_axil_wvalid, s_axil_wready=s_axil_wready, s_axil_bresp=s_axil_bresp, s_axil_bvalid=s_axil_bvalid, s_axil_bready=s_axil_bready, s_axil_araddr=s_axil_araddr, s_axil_arprot=s_axil_arprot, s_axil_arvalid=s_axil_arvalid, s_axil_arready=s_axil_arready, s_axil_rdata=s_axil_rdata, s_axil_rresp=s_axil_rresp, s_axil_rvalid=s_axil_rvalid, s_axil_rready=s_axil_rready, i2c_scl_i=i2c_scl_i, i2c_scl_o=i2c_scl_o, i2c_scl_t=i2c_scl_t, i2c_sda_i=i2c_sda_i, i2c_sda_o=i2c_sda_o, i2c_sda_t=i2c_sda_t) @always_comb def bus(): # emulate I2C wired AND scl = i2c_scl_o & s1_scl_o & s2_scl_o sda = i2c_sda_o & s1_sda_o & s2_sda_o i2c_scl_i.next = scl i2c_sda_i.next = sda s1_scl_i.next = scl s1_sda_i.next = sda s2_scl_i.next = scl s2_sda_i.next = sda @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: write") current_test.next = 1 axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x00') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x04') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x11') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x22') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x33') axil_master_inst.init_write(4, b'\x50\x14\x00\x00\x44') yield axil_master_inst.wait() yield clk.posedge while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x03 == 0: break data = i2c_mem_inst1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem_inst1.read_mem(4, 4) == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x00') axil_master_inst.init_write(4, b'\x50\x04\x00\x00\x04') axil_master_inst.init_write(4, b'\x50\x03') axil_master_inst.init_write(4, b'\x50\x02') axil_master_inst.init_write(4, b'\x50\x02') axil_master_inst.init_write(4, b'\x50\x12') yield axil_master_inst.wait() yield clk.posedge while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x03 == 0: break axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) yield axil_master_inst.wait() yield clk.posedge data = axil_master_inst.get_read_data() assert data[1] == b'\x11\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x22\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x33\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x44\x03' yield delay(100) yield clk.posedge print("test 3: write to slave 2") current_test.next = 3 axil_master_inst.init_write(4, b'\x51\x08\x00\x00\x00\x00') axil_master_inst.init_write(8, b'\x04\x00') axil_master_inst.init_write(8, b'\x44\x00') axil_master_inst.init_write(8, b'\x33\x00') axil_master_inst.init_write(8, b'\x22\x00') axil_master_inst.init_write(8, b'\x11\x02') axil_master_inst.init_write(4, b'\x51\x10') yield axil_master_inst.wait() yield clk.posedge while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x03 == 0: break data = i2c_mem_inst2.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem_inst2.read_mem(4, 4) == b'\x44\x33\x22\x11' yield delay(100) yield clk.posedge print("test 4: read from slave 2") current_test.next = 4 axil_master_inst.init_write(4, b'\x51\x04\x00\x00\x00') axil_master_inst.init_write(4, b'\x51\x04\x00\x00\x04') axil_master_inst.init_write(4, b'\x51\x03') axil_master_inst.init_write(4, b'\x51\x02') axil_master_inst.init_write(4, b'\x51\x02') axil_master_inst.init_write(4, b'\x51\x12') yield axil_master_inst.wait() yield clk.posedge while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x03 == 0: break axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) axil_master_inst.init_read(8, 2) yield axil_master_inst.wait() yield clk.posedge data = axil_master_inst.get_read_data() assert data[1] == b'\x44\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x33\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x22\x01' data = axil_master_inst.get_read_data() assert data[1] == b'\x11\x03' yield delay(100) yield clk.posedge print("test 5: write to nonexistent device") current_test.next = 5 axil_master_inst.init_write(4, b'\x52\x04\x00\x00\x00') axil_master_inst.init_write(4, b'\x52\x04\x00\x00\x04') axil_master_inst.init_write(4, b'\x52\x04\x00\x00\xde') axil_master_inst.init_write(4, b'\x52\x04\x00\x00\xad') axil_master_inst.init_write(4, b'\x52\x04\x00\x00\xbe') axil_master_inst.init_write(4, b'\x52\x14\x00\x00\xef') yield axil_master_inst.wait() yield clk.posedge got_missed_ack = False while True: axil_master_inst.init_read(0, 1) yield axil_master_inst.wait() data = axil_master_inst.get_read_data() if data[1][0] & 0x08: got_missed_ack = True if data[1][0] & 0x03 == 0: break assert got_missed_ack yield delay(100) raise StopSimulation return instances()
def bench(): # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) m_scl_i = Signal(bool(1)) m_sda_i = Signal(bool(1)) s1_scl_i = Signal(bool(1)) s1_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs m_scl_o = Signal(bool(1)) m_scl_t = Signal(bool(1)) m_sda_o = Signal(bool(1)) m_sda_t = Signal(bool(1)) s1_scl_o = Signal(bool(1)) s1_scl_t = Signal(bool(1)) s1_sda_o = Signal(bool(1)) s1_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # I2C master i2c_master_inst = i2c.I2CMaster() i2c_master_logic = i2c_master_inst.create_logic( clk, rst, scl_i=m_scl_i, scl_o=m_scl_o, scl_t=m_scl_t, sda_i=m_sda_i, sda_o=m_sda_o, sda_t=m_sda_t, prescale=2, name='master' ) # I2C memory model 1 i2c_mem_inst1 = i2c.I2CMem(1024) i2c_mem_logic1 = i2c_mem_inst1.create_logic( scl_i=s1_scl_i, scl_o=s1_scl_o, scl_t=s1_scl_t, sda_i=s1_sda_i, sda_o=s1_sda_o, sda_t=s1_sda_t, abw=2, address=0x50, latency=0, name='slave1' ) # I2C memory model 2 i2c_mem_inst2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem_inst2.create_logic( scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=1000, name='slave2' ) @always_comb def bus(): # emulate I2C wired AND m_scl_i.next = m_scl_o & s1_scl_o & s2_scl_o; m_sda_i.next = m_sda_o & s1_sda_o & s2_sda_o; s1_scl_i.next = m_scl_o & s1_scl_o & s2_scl_o; s1_sda_i.next = m_sda_o & s1_sda_o & s2_sda_o; s2_scl_i.next = m_scl_o & s1_scl_o & s2_scl_o; s2_sda_i.next = m_sda_o & s1_sda_o & s2_sda_o; @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge yield clk.posedge print("test 1: baseline") current_test.next = 1 data = i2c_mem_inst1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) yield delay(100) yield clk.posedge print("test 2: direct write") current_test.next = 2 i2c_mem_inst1.write_mem(0, b'test') data = i2c_mem_inst1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert i2c_mem_inst1.read_mem(0,4) == b'test' yield delay(100) yield clk.posedge print("test 3: write via I2C") current_test.next = 3 i2c_master_inst.init_write(0x50, b'\x00\x04'+b'\x11\x22\x33\x44') yield i2c_master_inst.wait() yield clk.posedge data = i2c_mem_inst1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert i2c_mem_inst1.read_mem(4,4) == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 4: read via I2C") current_test.next = 4 i2c_master_inst.init_write(0x50, b'\x00\x04') i2c_master_inst.init_read(0x50, 4) yield i2c_master_inst.wait() yield clk.posedge data = i2c_master_inst.get_read_data() assert data[0] == 0x50 assert data[1] == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 5: access slave 2") current_test.next = 3 i2c_master_inst.init_write(0x51, b'\x00\x04'+b'\x11\x22\x33\x44') yield i2c_master_inst.wait() yield clk.posedge data = i2c_mem_inst2.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert i2c_mem_inst2.read_mem(4,4) == b'\x11\x22\x33\x44' i2c_master_inst.init_write(0x51, b'\x00\x04') i2c_master_inst.init_read(0x51, 4) yield i2c_master_inst.wait() yield clk.posedge data = i2c_master_inst.get_read_data() assert data[0] == 0x51 assert data[1] == b'\x11\x22\x33\x44' yield delay(100) raise StopSimulation return i2c_master_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check
def bench(): # Parameters FILTER_LEN = 1 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) release_bus = Signal(bool(0)) data_in = Signal(intbv(0)[8:]) data_in_valid = Signal(bool(0)) data_in_last = Signal(bool(0)) data_out_ready = Signal(bool(0)) scl_i = Signal(bool(1)) sda_i = Signal(bool(1)) enable = Signal(bool(0)) device_address = Signal(intbv(0)[7:]) device_address_mask = Signal(intbv(0x7f)[7:]) m_scl_i = Signal(bool(1)) m_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs data_in_ready = Signal(bool(0)) data_out = Signal(intbv(0)[8:]) data_out_valid = Signal(bool(0)) data_out_last = Signal(bool(0)) scl_o = Signal(bool(1)) scl_t = Signal(bool(1)) sda_o = Signal(bool(1)) sda_t = Signal(bool(1)) busy = Signal(bool(0)) bus_address = Signal(intbv(0)[7:]) bus_addressed = Signal(bool(0)) bus_active = Signal(bool(0)) m_scl_o = Signal(bool(1)) m_scl_t = Signal(bool(1)) m_sda_o = Signal(bool(1)) m_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # sources and sinks data_source_pause = Signal(bool(0)) data_sink_pause = Signal(bool(0)) data_source = axis_ep.AXIStreamSource() data_source_logic = data_source.create_logic( clk, rst, tdata=data_in, tvalid=data_in_valid, tready=data_in_ready, tlast=data_in_last, pause=data_source_pause, name='data_source' ) data_sink = axis_ep.AXIStreamSink() data_sink_logic = data_sink.create_logic( clk, rst, tdata=data_out, tvalid=data_out_valid, tready=data_out_ready, tlast=data_out_last, pause=data_sink_pause, name='data_sink' ) # I2C master i2c_master_inst = i2c.I2CMaster() i2c_master_logic = i2c_master_inst.create_logic( clk, rst, scl_i=m_scl_i, scl_o=m_scl_o, scl_t=m_scl_t, sda_i=m_sda_i, sda_o=m_sda_o, sda_t=m_sda_t, prescale=4, name='master' ) # I2C memory model 2 i2c_mem_inst2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem_inst2.create_logic( scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=0, name='slave2' ) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, release_bus=release_bus, data_in=data_in, data_in_valid=data_in_valid, data_in_ready=data_in_ready, data_in_last=data_in_last, data_out=data_out, data_out_valid=data_out_valid, data_out_ready=data_out_ready, data_out_last=data_out_last, scl_i=scl_i, scl_o=scl_o, scl_t=scl_t, sda_i=sda_i, sda_o=sda_o, sda_t=sda_t, busy=busy, bus_address=bus_address, bus_addressed=bus_addressed, bus_active=bus_active, enable=enable, device_address=device_address, device_address_mask=device_address_mask ) @always_comb def bus(): # emulate I2C wired AND m_scl_i.next = m_scl_o & scl_o & s2_scl_o; m_sda_i.next = m_sda_o & sda_o & s2_sda_o; scl_i.next = m_scl_o & scl_o & s2_scl_o; sda_i.next = m_sda_o & sda_o & s2_sda_o; s2_scl_i.next = m_scl_o & scl_o & s2_scl_o; s2_sda_i.next = m_sda_o & sda_o & s2_sda_o; @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus enable.next = 1 device_address.next = 0x50 device_address_mask.next = 0x7f yield clk.posedge print("test 1: write") current_test.next = 1 i2c_master_inst.init_write(0x50, b'\x00\x04'+b'\x11\x22\x33\x44') yield i2c_master_inst.wait() yield clk.posedge data = None while not data: yield clk.posedge data = data_sink.recv() assert data.data == b'\x00\x04'+b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 i2c_master_inst.init_write(0x50, b'\x00\x04') i2c_master_inst.init_read(0x50, 4) data_source.send(b'\x11\x22\x33\x44') yield i2c_master_inst.wait() yield clk.posedge data = None while not data: yield clk.posedge data = data_sink.recv() assert data.data == b'\x00\x04' data = i2c_master_inst.get_read_data() assert data[0] == 0x50 assert data[1] == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 3: read with delays") current_test.next = 3 i2c_master_inst.init_write(0x50, b'\x00\x04') i2c_master_inst.init_read(0x50, 4) data_source.send(b'\x11\x22\x33\x44') data_source_pause.next = True data_sink_pause.next = True yield delay(5000) data_sink_pause.next = False yield delay(2000) data_source_pause.next = False yield i2c_master_inst.wait() yield clk.posedge data = None while not data: yield clk.posedge data = data_sink.recv() assert data.data == b'\x00\x04' data = i2c_master_inst.get_read_data() assert data[0] == 0x50 assert data[1] == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 4: access slave 2") current_test.next = 4 i2c_master_inst.init_write(0x51, b'\x00\x04'+b'\x11\x22\x33\x44') yield i2c_master_inst.wait() yield clk.posedge data = i2c_mem_inst2.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert i2c_mem_inst2.read_mem(4,4) == b'\x11\x22\x33\x44' i2c_master_inst.init_write(0x51, b'\x00\x04') i2c_master_inst.init_read(0x51, 4) yield i2c_master_inst.wait() yield clk.posedge data = i2c_master_inst.get_read_data() assert data[0] == 0x51 assert data[1] == b'\x11\x22\x33\x44' yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) cmd_address = Signal(intbv(0)[7:]) cmd_start = Signal(bool(0)) cmd_read = Signal(bool(0)) cmd_write = Signal(bool(0)) cmd_write_multiple = Signal(bool(0)) cmd_stop = Signal(bool(0)) cmd_valid = Signal(bool(0)) data_in = Signal(intbv(0)[8:]) data_in_valid = Signal(bool(0)) data_in_last = Signal(bool(0)) data_out_ready = Signal(bool(0)) scl_i = Signal(bool(1)) sda_i = Signal(bool(1)) prescale = Signal(intbv(0)[16:]) stop_on_idle = Signal(bool(0)) s1_scl_i = Signal(bool(1)) s1_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs cmd_ready = Signal(bool(0)) data_in_ready = Signal(bool(0)) data_out = Signal(intbv(0)[8:]) data_out_valid = Signal(bool(0)) data_out_last = Signal(bool(0)) scl_o = Signal(bool(1)) scl_t = Signal(bool(1)) sda_o = Signal(bool(1)) sda_t = Signal(bool(1)) busy = Signal(bool(0)) bus_control = Signal(bool(0)) bus_active = Signal(bool(0)) missed_ack = Signal(bool(0)) s1_scl_o = Signal(bool(1)) s1_scl_t = Signal(bool(1)) s1_sda_o = Signal(bool(1)) s1_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # sources and sinks cmd_source_pause = Signal(bool(0)) data_source_pause = Signal(bool(0)) data_sink_pause = Signal(bool(0)) cmd_source = axis_ep.AXIStreamSource() cmd_source_logic = cmd_source.create_logic( clk, rst, tdata=(cmd_address, cmd_start, cmd_read, cmd_write, cmd_write_multiple, cmd_stop), tvalid=cmd_valid, tready=cmd_ready, pause=cmd_source_pause, name='cmd_source') data_source = axis_ep.AXIStreamSource() data_source_logic = data_source.create_logic(clk, rst, tdata=data_in, tvalid=data_in_valid, tready=data_in_ready, tlast=data_in_last, pause=data_source_pause, name='data_source') data_sink = axis_ep.AXIStreamSink() data_sink_logic = data_sink.create_logic(clk, rst, tdata=data_out, tvalid=data_out_valid, tready=data_out_ready, tlast=data_out_last, pause=data_sink_pause, name='data_sink') # I2C memory model 1 i2c_mem_inst1 = i2c.I2CMem(1024) i2c_mem_logic1 = i2c_mem_inst1.create_logic(scl_i=s1_scl_i, scl_o=s1_scl_o, scl_t=s1_scl_t, sda_i=s1_sda_i, sda_o=s1_sda_o, sda_t=s1_sda_t, abw=2, address=0x50, latency=0, name='slave1') # I2C memory model 2 i2c_mem_inst2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem_inst2.create_logic(scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=1000, name='slave2') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, cmd_address=cmd_address, cmd_start=cmd_start, cmd_read=cmd_read, cmd_write=cmd_write, cmd_write_multiple=cmd_write_multiple, cmd_stop=cmd_stop, cmd_valid=cmd_valid, cmd_ready=cmd_ready, data_in=data_in, data_in_valid=data_in_valid, data_in_ready=data_in_ready, data_in_last=data_in_last, data_out=data_out, data_out_valid=data_out_valid, data_out_ready=data_out_ready, data_out_last=data_out_last, scl_i=scl_i, scl_o=scl_o, scl_t=scl_t, sda_i=sda_i, sda_o=sda_o, sda_t=sda_t, busy=busy, bus_control=bus_control, bus_active=bus_active, missed_ack=missed_ack, prescale=prescale, stop_on_idle=stop_on_idle) @always_comb def bus(): # emulate I2C wired AND scl_i.next = scl_o & s1_scl_o & s2_scl_o sda_i.next = sda_o & s1_sda_o & s2_sda_o s1_scl_i.next = scl_o & s1_scl_o & s2_scl_o s1_sda_i.next = sda_o & s1_sda_o & s2_sda_o s2_scl_i.next = scl_o & s1_scl_o & s2_scl_o s2_sda_i.next = sda_o & s1_sda_o & s2_sda_o @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge prescale.next = 2 yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: write") current_test.next = 1 cmd_source.send([( 0x50, # address 0, # start 0, # read 0, # write 1, # write_multiple 1 # stop )]) data_source.send((b'\x00\x04' + b'\x11\x22\x33\x44')) yield clk.posedge yield clk.posedge yield clk.posedge while busy or bus_active or not cmd_source.empty(): yield clk.posedge yield clk.posedge data = i2c_mem_inst1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem_inst1.read_mem(4, 4) == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 cmd_source.send([( 0x50, # address 0, # start 0, # read 0, # write 1, # write_multiple 0 # stop )]) data_source.send((b'\x00\x04')) for i in range(3): cmd_source.send([( 0x50, # address 0, # start 1, # read 0, # write 0, # write_multiple 0 # stop )]) cmd_source.send([( 0x50, # address 0, # start 1, # read 0, # write 0, # write_multiple 1 # stop )]) yield clk.posedge yield clk.posedge yield clk.posedge while busy or bus_active or not cmd_source.empty(): yield clk.posedge yield clk.posedge data = data_sink.recv() assert data.data == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 3: write to slave 2") current_test.next = 3 cmd_source.send([( 0x51, # address 0, # start 0, # read 0, # write 1, # write_multiple 1 # stop )]) data_source.send((b'\x00\x04' + b'\x44\x33\x22\x11')) yield clk.posedge yield clk.posedge yield clk.posedge while busy or bus_active or not cmd_source.empty(): yield clk.posedge yield clk.posedge data = i2c_mem_inst1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem_inst2.read_mem(4, 4) == b'\x44\x33\x22\x11' yield delay(100) yield clk.posedge print("test 4: read from slave 2") current_test.next = 4 cmd_source.send([( 0x51, # address 0, # start 0, # read 0, # write 1, # write_multiple 0 # stop )]) data_source.send((b'\x00\x04')) for i in range(3): cmd_source.send([( 0x51, # address 0, # start 1, # read 0, # write 0, # write_multiple 0 # stop )]) cmd_source.send([( 0x51, # address 0, # start 1, # read 0, # write 0, # write_multiple 1 # stop )]) yield clk.posedge yield clk.posedge yield clk.posedge while busy or bus_active or not cmd_source.empty(): yield clk.posedge yield clk.posedge data = data_sink.recv() assert data.data == b'\x44\x33\x22\x11' yield delay(100) yield clk.posedge print("test 5: write to nonexistent device") current_test.next = 5 cmd_source.send([( 0x52, # address 0, # start 0, # read 0, # write 1, # write_multiple 1 # stop )]) data_source.send((b'\x00\x04' + b'\xde\xad\xbe\xef')) got_missed_ack = False for k in range(1000): got_missed_ack |= missed_ack yield clk.posedge assert got_missed_ack yield clk.posedge yield clk.posedge yield clk.posedge while busy or bus_active or not cmd_source.empty(): yield clk.posedge yield clk.posedge yield delay(100) raise StopSimulation return dut, cmd_source_logic, data_source_logic, data_sink_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check
def bench(): # Parameters FILTER_LEN = 4 DATA_WIDTH = 32 ADDR_WIDTH = 16 STRB_WIDTH = (DATA_WIDTH/8) # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) i2c_scl_i = Signal(bool(1)) i2c_sda_i = Signal(bool(1)) m_axil_awready = Signal(bool(0)) m_axil_wready = Signal(bool(0)) m_axil_bresp = Signal(intbv(0)[2:]) m_axil_bvalid = Signal(bool(0)) m_axil_arready = Signal(bool(0)) m_axil_rdata = Signal(intbv(0)[DATA_WIDTH:]) m_axil_rresp = Signal(intbv(0)[2:]) m_axil_rvalid = Signal(bool(0)) enable = Signal(bool(0)) device_address = Signal(intbv(0)[7:]) m_scl_i = Signal(bool(1)) m_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs i2c_scl_o = Signal(bool(1)) i2c_scl_t = Signal(bool(1)) i2c_sda_o = Signal(bool(1)) i2c_sda_t = Signal(bool(1)) m_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:]) m_axil_awprot = Signal(intbv(0)[3:]) m_axil_awvalid = Signal(bool(0)) m_axil_wdata = Signal(intbv(0)[DATA_WIDTH:]) m_axil_wstrb = Signal(intbv(0)[STRB_WIDTH:]) m_axil_wvalid = Signal(bool(0)) m_axil_bready = Signal(bool(0)) m_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:]) m_axil_arprot = Signal(intbv(0)[3:]) m_axil_arvalid = Signal(bool(0)) m_axil_rready = Signal(bool(0)) busy = Signal(bool(0)) bus_addressed = Signal(bool(0)) bus_active = Signal(bool(0)) m_scl_o = Signal(bool(1)) m_scl_t = Signal(bool(1)) m_sda_o = Signal(bool(1)) m_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # I2C master i2c_master_inst = i2c.I2CMaster() i2c_master_logic = i2c_master_inst.create_logic( clk, rst, scl_i=m_scl_i, scl_o=m_scl_o, scl_t=m_scl_t, sda_i=m_sda_i, sda_o=m_sda_o, sda_t=m_sda_t, prescale=4, name='master' ) # I2C memory model 2 i2c_mem_inst2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem_inst2.create_logic( scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=0, name='slave2' ) # AXI4-Lite RAM model axil_ram_inst = axil.AXILiteRam(2**16) axil_ram_pause = Signal(bool(False)) axil_ram_port0 = axil_ram_inst.create_port( clk, s_axil_awaddr=m_axil_awaddr, s_axil_awprot=m_axil_awprot, s_axil_awvalid=m_axil_awvalid, s_axil_awready=m_axil_awready, s_axil_wdata=m_axil_wdata, s_axil_wstrb=m_axil_wstrb, s_axil_wvalid=m_axil_wvalid, s_axil_wready=m_axil_wready, s_axil_bresp=m_axil_bresp, s_axil_bvalid=m_axil_bvalid, s_axil_bready=m_axil_bready, s_axil_araddr=m_axil_araddr, s_axil_arprot=m_axil_arprot, s_axil_arvalid=m_axil_arvalid, s_axil_arready=m_axil_arready, s_axil_rdata=m_axil_rdata, s_axil_rresp=m_axil_rresp, s_axil_rvalid=m_axil_rvalid, s_axil_rready=m_axil_rready, pause=axil_ram_pause, name='port0' ) # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation( "vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, i2c_scl_i=i2c_scl_i, i2c_scl_o=i2c_scl_o, i2c_scl_t=i2c_scl_t, i2c_sda_i=i2c_sda_i, i2c_sda_o=i2c_sda_o, i2c_sda_t=i2c_sda_t, m_axil_awaddr=m_axil_awaddr, m_axil_awprot=m_axil_awprot, m_axil_awvalid=m_axil_awvalid, m_axil_awready=m_axil_awready, m_axil_wdata=m_axil_wdata, m_axil_wstrb=m_axil_wstrb, m_axil_wvalid=m_axil_wvalid, m_axil_wready=m_axil_wready, m_axil_bresp=m_axil_bresp, m_axil_bvalid=m_axil_bvalid, m_axil_bready=m_axil_bready, m_axil_araddr=m_axil_araddr, m_axil_arprot=m_axil_arprot, m_axil_arvalid=m_axil_arvalid, m_axil_arready=m_axil_arready, m_axil_rdata=m_axil_rdata, m_axil_rresp=m_axil_rresp, m_axil_rvalid=m_axil_rvalid, m_axil_rready=m_axil_rready, busy=busy, bus_addressed=bus_addressed, bus_active=bus_active, enable=enable, device_address=device_address ) @always_comb def bus(): # emulate I2C wired AND scl = m_scl_o & i2c_scl_o & s2_scl_o sda = m_sda_o & i2c_sda_o & s2_sda_o m_scl_i.next = scl; m_sda_i.next = sda; i2c_scl_i.next = scl i2c_sda_i.next = sda s2_scl_i.next = scl s2_sda_i.next = sda @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus enable.next = 1 device_address.next = 0x50 yield clk.posedge print("test 1: write") current_test.next = 1 i2c_master_inst.init_write(0x50, b'\x00\x04'+b'\x11\x22\x33\x44') yield i2c_master_inst.wait() yield clk.posedge while busy: yield clk.posedge data = axil_ram_inst.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert axil_ram_inst.read_mem(4,4) == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 i2c_master_inst.init_write(0x50, b'\x00\x04') i2c_master_inst.init_read(0x50, 4) yield i2c_master_inst.wait() yield clk.posedge data = i2c_master_inst.get_read_data() assert data[0] == 0x50 assert data[1] == b'\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 3: various writes") current_test.next = 3 for length in range(1,9): for offset in range(4): i2c_master_inst.init_write(0x50, bytearray(struct.pack('>H', 256*(16*offset+length)+offset)+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])) yield i2c_master_inst.wait() yield clk.posedge while busy: yield clk.posedge data = axil_ram_inst.read_mem(256*(16*offset+length), 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert axil_ram_inst.read_mem(256*(16*offset+length)+offset,length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] yield delay(100) yield clk.posedge print("test 4: various reads") current_test.next = 4 for length in range(1,9): for offset in range(4): i2c_master_inst.init_write(0x50, bytearray(struct.pack('>H', 256*(16*offset+length)+offset))) i2c_master_inst.init_read(0x50, length) yield i2c_master_inst.wait() yield clk.posedge data = i2c_master_inst.get_read_data() assert data[0] == 0x50 assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] yield delay(100) # TODO various reads and writes # yield clk.posedge # print("test 3: read with delays") # current_test.next = 3 # i2c_master_inst.init_write(0x50, b'\x00\x04') # i2c_master_inst.init_read(0x50, 4) # data_source.send(b'\x11\x22\x33\x44') # data_source_pause.next = True # data_sink_pause.next = True # yield delay(5000) # data_sink_pause.next = False # yield delay(2000) # data_source_pause.next = False # yield i2c_master_inst.wait() # yield clk.posedge # data = None # while not data: # yield clk.posedge # data = data_sink.recv() # assert data.data == b'\x00\x04' # data = i2c_master_inst.get_read_data() # assert data[0] == 0x50 # assert data[1] == b'\x11\x22\x33\x44' # yield delay(100) yield clk.posedge print("test 4: access slave 2") current_test.next = 4 i2c_master_inst.init_write(0x51, b'\x00\x04'+b'\x11\x22\x33\x44') yield i2c_master_inst.wait() yield clk.posedge data = i2c_mem_inst2.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16])))) assert i2c_mem_inst2.read_mem(4,4) == b'\x11\x22\x33\x44' i2c_master_inst.init_write(0x51, b'\x00\x04') i2c_master_inst.init_read(0x51, 4) yield i2c_master_inst.wait() yield clk.posedge data = i2c_master_inst.get_read_data() assert data[0] == 0x51 assert data[1] == b'\x11\x22\x33\x44' yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters XFCP_ID_TYPE = 0x2C00 XFCP_ID_STR = "I2C Master" XFCP_EXT_ID = 0 XFCP_EXT_ID_STR = "" DEFAULT_PRESCALE = 1 # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) up_xfcp_in_tdata = Signal(intbv(0)[8:]) up_xfcp_in_tvalid = Signal(bool(0)) up_xfcp_in_tlast = Signal(bool(0)) up_xfcp_in_tuser = Signal(bool(0)) up_xfcp_out_tready = Signal(bool(0)) i2c_scl_i = Signal(bool(1)) i2c_sda_i = Signal(bool(1)) s1_scl_i = Signal(bool(1)) s1_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs up_xfcp_in_tready = Signal(bool(0)) up_xfcp_out_tdata = Signal(intbv(0)[8:]) up_xfcp_out_tvalid = Signal(bool(0)) up_xfcp_out_tlast = Signal(bool(0)) up_xfcp_out_tuser = Signal(bool(0)) i2c_scl_o = Signal(bool(1)) i2c_scl_t = Signal(bool(1)) i2c_sda_o = Signal(bool(1)) i2c_sda_t = Signal(bool(1)) s1_scl_o = Signal(bool(1)) s1_scl_t = Signal(bool(1)) s1_sda_o = Signal(bool(1)) s1_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # XFCP ports up_xfcp_port_out_pause = Signal(bool(0)) up_xfcp_port_in_pause = Signal(bool(0)) up_xfcp_port = xfcp.XFCPPort() up_xfcp_port_logic = up_xfcp_port.create_logic( clk=clk, rst=rst, xfcp_in_tdata=up_xfcp_out_tdata, xfcp_in_tvalid=up_xfcp_out_tvalid, xfcp_in_tready=up_xfcp_out_tready, xfcp_in_tlast=up_xfcp_out_tlast, xfcp_in_tuser=up_xfcp_out_tuser, xfcp_out_tdata=up_xfcp_in_tdata, xfcp_out_tvalid=up_xfcp_in_tvalid, xfcp_out_tready=up_xfcp_in_tready, xfcp_out_tlast=up_xfcp_in_tlast, xfcp_out_tuser=up_xfcp_in_tuser, pause_source=up_xfcp_port_in_pause, pause_sink=up_xfcp_port_out_pause, name='up_xfcp_port') # I2C memory model 1 i2c_mem1 = i2c.I2CMem(1024) i2c_mem_logic1 = i2c_mem1.create_logic(scl_i=s1_scl_i, scl_o=s1_scl_o, scl_t=s1_scl_t, sda_i=s1_sda_i, sda_o=s1_sda_o, sda_t=s1_sda_t, abw=2, address=0x50, latency=0, name='slave1') # I2C memory model 2 i2c_mem2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem2.create_logic(scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=1000, name='slave2') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, up_xfcp_in_tdata=up_xfcp_in_tdata, up_xfcp_in_tvalid=up_xfcp_in_tvalid, up_xfcp_in_tready=up_xfcp_in_tready, up_xfcp_in_tlast=up_xfcp_in_tlast, up_xfcp_in_tuser=up_xfcp_in_tuser, up_xfcp_out_tdata=up_xfcp_out_tdata, up_xfcp_out_tvalid=up_xfcp_out_tvalid, up_xfcp_out_tready=up_xfcp_out_tready, up_xfcp_out_tlast=up_xfcp_out_tlast, up_xfcp_out_tuser=up_xfcp_out_tuser, i2c_scl_i=i2c_scl_i, i2c_scl_o=i2c_scl_o, i2c_scl_t=i2c_scl_t, i2c_sda_i=i2c_sda_i, i2c_sda_o=i2c_sda_o, i2c_sda_t=i2c_sda_t) @always_comb def bus(): # emulate I2C wired AND i2c_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o i2c_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o s1_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o s1_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o s2_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o s2_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o @always(delay(4)) def clkgen(): clk.next = not clk def wait_normal(): i = 8 while i > 0: i = max(0, i - 1) if not up_xfcp_port.idle() or not i2c_scl_i or not i2c_sda_i: i = 8 yield clk.posedge def wait_pause_source(): i = 4 while i > 0: i = max(0, i - 1) if not up_xfcp_port.idle() or not i2c_scl_i or not i2c_sda_i: i = 4 up_xfcp_port_in_pause.next = True yield clk.posedge yield clk.posedge yield clk.posedge up_xfcp_port_in_pause.next = False yield clk.posedge def wait_pause_sink(): i = 4 while i > 0: i = max(0, i - 1) if not up_xfcp_port.idle() or not i2c_scl_i or not i2c_sda_i: i = 4 up_xfcp_port_out_pause.next = True yield clk.posedge yield clk.posedge yield clk.posedge up_xfcp_port_out_pause.next = False yield clk.posedge @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: write") current_test.next = 1 pkt = xfcp.XFCPFrame() pkt.ptype = 0x2C pkt.payload = b'\xD0\x1C\x06\x00\x04\x11\x22\x33\x44' for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt) yield clk.posedge yield wait() yield clk.posedge data = i2c_mem1.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem1.read_mem(4, 4) == b'\x11\x22\x33\x44' rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.ptype == 0x2D assert rx_pkt.payload.data == b'\xD0\x1C\x06\x00\x04\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 2: read") current_test.next = 2 pkt = xfcp.XFCPFrame() pkt.ptype = 0x2C pkt.payload = b'\xD0\x14\x02\x00\x04\x1A\x04' for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt) yield clk.posedge yield wait() yield clk.posedge rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.ptype == 0x2D assert rx_pkt.payload.data == b'\xD0\x14\x02\x00\x04\x1A\x04\x11\x22\x33\x44' yield delay(100) yield clk.posedge print("test 3: write to slave 2") current_test.next = 3 pkt = xfcp.XFCPFrame() pkt.ptype = 0x2C pkt.payload = b'\xD1\x04\x00\x04\x04\x04\x44\x04\x33\x04\x22\x0C\x11' for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt) yield clk.posedge yield wait() yield clk.posedge data = i2c_mem2.read_mem(0, 32) for i in range(0, len(data), 16): print(" ".join( ("{:02x}".format(c) for c in bytearray(data[i:i + 16])))) assert i2c_mem2.read_mem(4, 4) == b'\x44\x33\x22\x11' rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.ptype == 0x2D assert rx_pkt.payload.data == b'\xD1\x04\x00\x04\x04\x04\x44\x04\x33\x04\x22\x0C\x11' yield delay(100) yield clk.posedge print("test 4: read from slave 2") current_test.next = 4 pkt = xfcp.XFCPFrame() pkt.ptype = 0x2C pkt.payload = b'\xD1\x04\x00\x04\x04\x02\x02\x02\x0A' for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt) yield clk.posedge yield wait() yield clk.posedge rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.ptype == 0x2D assert rx_pkt.payload.data == b'\xD1\x04\x00\x04\x04\x02\x44\x02\x33\x02\x22\x0A\x11' yield delay(100) yield clk.posedge print("test 5: test configuration and status") current_test.next = 5 pkt = xfcp.XFCPFrame() pkt.ptype = 0x2C pkt.payload = b'\x60\x04\x00\x60\x01\x00\x40' for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt) yield clk.posedge yield wait() yield clk.posedge rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.ptype == 0x2D assert rx_pkt.payload.data == b'\x60\x04\x00\x60\x01\x00\x40\x00' yield delay(100) yield clk.posedge print("test 6: test id") current_test.next = 6 pkt = xfcp.XFCPFrame() pkt.ptype = 0xFE pkt.payload = b'' for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt) yield clk.posedge yield wait() yield clk.posedge rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.ptype == 0xff assert len(rx_pkt.payload.data) == 32 yield delay(100) yield clk.posedge print("test 7: test id with trailing bytes") current_test.next = 7 pkt1 = xfcp.XFCPFrame() pkt1.ptype = 0xFE pkt1.payload = b'\0' * 256 pkt2 = xfcp.XFCPFrame() pkt2.ptype = 0xFE pkt2.payload = b'\0' * 8 for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt1) up_xfcp_port.send(pkt2) yield clk.posedge yield wait() yield clk.posedge rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.ptype == 0xff assert len(rx_pkt.payload.data) == 32 rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.ptype == 0xff assert len(rx_pkt.payload.data) == 32 yield delay(100) yield clk.posedge print("test 8: test with rpath") current_test.next = 8 pkt1 = xfcp.XFCPFrame() pkt1.rpath = [1, 2, 3] pkt1.ptype = 0xFE pkt1.payload = b'\0' * 8 pkt2 = xfcp.XFCPFrame() pkt2.rpath = [4, 5, 6] pkt2.ptype = 0x2C pkt2.payload = b'\xD0\x04\x00\x04\x04\x02\x02\x02\x0A' for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt1) up_xfcp_port.send(pkt2) yield clk.posedge yield wait() yield clk.posedge rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.rpath == [1, 2, 3] assert rx_pkt.ptype == 0xff assert len(rx_pkt.payload.data) == 32 rx_pkt = up_xfcp_port.recv() print(rx_pkt) assert rx_pkt.rpath == [4, 5, 6] assert rx_pkt.ptype == 0x2D assert rx_pkt.payload.data == b'\xD0\x04\x00\x04\x04\x02\x11\x02\x22\x02\x33\x0A\x44' yield delay(100) yield clk.posedge print("test 9: test invalid packets") current_test.next = 9 pkt1 = xfcp.XFCPFrame() pkt1.ptype = 0x99 pkt1.payload = b'\x00' * 8 pkt2 = xfcp.XFCPFrame() pkt2.path = [0] pkt2.ptype = 0xFE pkt2.payload = b'' for wait in wait_normal, wait_pause_source, wait_pause_sink: up_xfcp_port.send(pkt1) up_xfcp_port.send(pkt2) yield clk.posedge yield wait() yield clk.posedge rx_pkt = up_xfcp_port.recv() assert rx_pkt is None yield delay(100) raise StopSimulation return instances()