def bench_rle_conversion(): width = 6 constants = Constants(width_addr=width, width_data=12, max_write_cnt=63, rlength=4, size=width.bit_length()) clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) indatastream = InDataStream(constants.width_data) bufferdatabus = BufferDataBus( constants.width_data, constants.size, constants.rlength) rleconfig = RLEConfig(constants.max_write_cnt.bit_length()) width_dbuf = constants.width_data + constants.size + constants.rlength dfifo_const = Constants(width=width_dbuf, depth=constants.max_write_cnt + 1) inst = rlencoder( dfifo_const, constants, reset, clock, indatastream, bufferdatabus, rleconfig) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] if ycbcr.data_valid == 1: # expected_outputs signal assignment y_s.next = exp_y[i - 3] cb_s.next = exp_cb[i - 3] cr_s.next = exp_cr[i - 3] yield delay(1) print("Expected outputs ===>Y:%d Cb:%d Cr:%d" % (y_s, cb_s, cr_s)) print("Actual outputs ===>Y:%d Cb:%d Cr:%d" % (ycbcr.y, ycbcr.cb, ycbcr.cr)) print("----------------------------") yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim, tbrst
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] if ycbcr.data_valid == 1: # expected_outputs signal assignment y_s.next = exp_y[i-3] cb_s.next = exp_cb[i-3] cr_s.next = exp_cr[i-3] yield delay(1) print("Expected outputs ===>Y:%d Cb:%d Cr:%d" % (y_s, cb_s, cr_s)) print("Actual outputs ===>Y:%d Cb:%d Cr:%d" % (ycbcr.y, ycbcr.cb, ycbcr.cr)) print("----------------------------") yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim, tbrst
def bench_entropycoder(): inst = entropycoder(width, clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_zig_zag(): tdut = zig_zag(inputs, outputs, clock, reset, N) tbclock = clock_driver(clock) tbrst = reset_on_start(reset, clock) print_sig = [ Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2) ] print_sig_1 = [ Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2) ] in_sigs = [ Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2) ] @instance def tbstim(): inputs.data_valid.next = True for i in range(samples): for j in range(N**2): in_sigs[j].next = inputs_rom[i * (N**2) + j] yield clock.posedge print_assign = assign_array(print_sig_1, outputs.out_sigs) input_assign = assign_array(inputs.out_sigs, in_sigs) @instance def monitor(): outputs_count = 0 yield outputs.data_valid.posedge yield delay(1) while (outputs_count != samples): for i in range(N**2): print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i] yield delay(1) print("Expected Outputs") for i in range(N**2): print("%d " % print_sig[i]) print("Actual Outputs") for i in range(N**2): print("%d " % print_sig_1[i]) print("------------------------------") outputs_count += 1 yield clock.posedge raise StopSimulation return tdut, tbclock, tbstim, monitor, print_assign, input_assign, tbrst
def bench_rle_core(): """The conversion module for rle core""" inst = rle( clock, reset, datastream, rlesymbols, rleconfig ) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy inputs for conversion purpose""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = bytestuffer(clock, reset, bs_in_stream, bs_out_stream, bs_cntrl, num_enc_bytes) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_zig_zag(): tdut = zig_zag(inputs, outputs, clock, reset, N) tbclock = clock_driver(clock) tbrst = reset_on_start(reset, clock) print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] in_sigs = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] @instance def tbstim(): inputs.data_valid.next = True for i in range(samples): for j in range(N**2): in_sigs[j].next = inputs_rom[i*(N**2) + j] yield clock.posedge print_assign = assign_array(print_sig_1, outputs.out_sigs) input_assign = assign_array(inputs.out_sigs, in_sigs) @instance def monitor(): outputs_count = 0 yield outputs.data_valid.posedge yield delay(1) while(outputs_count != samples): for i in range(N**2): print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i] yield delay(1) print("Expected Outputs") for i in range(N**2): print("%d " % print_sig[i]) print("Actual Outputs") for i in range(N**2): print("%d " % print_sig_1[i]) print("------------------------------") outputs_count += 1 yield clock.posedge raise StopSimulation return tdut, tbclock, tbstim, monitor, print_assign, input_assign, tbrst
def bench_doublebuffer_conversion(): """test bench for conversion""" clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) buffer_sel = Signal(bool(0)) width_data = 20 width_depth = 64 # instantiation of fifo-bus, clock and rledoublefifo dfifo_bus = FIFOBus(width=width_data) inst = doublefifo(clock, reset, dfifo_bus, buffer_sel, depth=width_depth) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """some tests for conversion purpose""" # select first buffer buffer_sel.next = False yield clock.posedge # write first data into double buffer dfifo_bus.write.next = True # convert signed number to unsigned dfifo_bus.write_data.next = 3 yield clock.posedge dfifo_bus.write.next = False yield clock.posedge assert dfifo_bus.empty yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_frontend(): print_sig = Signal(intbv(0, min=-outputs.out_range, max=outputs.out_range)) tdut = frontend_top_level_v2(inputs, outputs, clock, reset) tbclock = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge inputs.data_valid.next = True for i in range(samples): for n in range(3): for j in range(64 * i, 64 * (i + 1)): inputs.red.next = r_rom[j] inputs.green.next = g_rom[j] inputs.blue.next = b_rom[j] yield clock.posedge @instance def monitor(): samples_count = 0 outputs_count = 0 clock_cycle_counter = 0 yield outputs.data_valid.posedge while(samples_count < samples): print("Processing Block %d" % (samples_count)) for i in range(3): while(outputs_count != 64): if i == 0: print_sig.next = y_out_rom[outputs_count + samples_count*64] elif i == 1: print_sig.next = cb_out_rom[outputs_count + samples_count*64] else: print_sig.next = cr_out_rom[outputs_count + samples_count*64] yield delay(1) print("%d %d" % (outputs.data_out, print_sig)) outputs_count += 1 clock_cycle_counter += 1 yield clock.posedge outputs_count = 0 samples_count += 1 raise StopSimulation return tdut, tbclock, tbstim, monitor, tbrst
def bench_dct_2d(): tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, output_bits, stage_1_prec, N) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] @instance def tbstim(): yield reset.negedge inputs.data_valid.next =True for i in range(samples * (N**2)): inputs.data_in.next = inputs_rom[i] yield clock.posedge print_assign = outputs.assignment_2(print_sig_1) @instance def monitor(): outputs_count = 0 while outputs_count != samples: yield clock.posedge if outputs.data_valid: for i in range(N**2): print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i] yield delay(1) print("Expected Outputs") for i in range(N**2): print("%d " % print_sig[i]) print("Actual Outputs") for i in range(N**2): print("%d " % print_sig_1[i]) print("------------------------------") outputs_count += 1 raise StopSimulation return tdut, tbclk, tbstim, monitor, tbrst, print_assign
def bench_dct_2d(): tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, output_bits, stage_1_prec, N) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits)) for _ in range(N**2)] @instance def tbstim(): yield reset.negedge inputs.data_valid.next =True for i in range(samples * (N**2)): inputs.data_in.next = inputs_rom[i] yield clock.posedge print_assign = assign_array(print_sig_1, outputs.out_sigs) @instance def monitor(): outputs_count = 0 while outputs_count != samples: yield clock.posedge if outputs.data_valid: for i in range(N**2): print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i] yield delay(1) print("Expected Outputs") for i in range(N**2): print("%d " % print_sig[i]) print("Actual Outputs") for i in range(N**2): print("%d " % print_sig_1[i]) print("------------------------------") outputs_count += 1 raise StopSimulation return tdut, tbclk, tbstim, monitor, tbrst, print_assign
def bench_quant_core(): """wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = quantizer_core(clock, reset, quant_output_stream, quant_input_stream, color_component) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests to convert the module""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_divider(): """Wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """Dummy tests to convert the module""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = huffman(clock, reset, huffmancntrl, bufferdatabus, huffmandatastream, img_size, rle_fifo_empty) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_quant_top_core(): """wrapper used for conversion purpose""" # instantiatiom of quantizer, clock and reset inst = quantizer(clock, reset, quanti_datastream, quant_ctrl, quanto_datastream) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests to convert the module""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = huffman(clock, reset, huffmancntrl, bufferdatabus, huffmandatastream, img_size, rle_fifo_empty) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_backend_conversion(): """This bench is used to test the functionality""" # instantiate module and clock inst = backend(clock, reset, start_block, data_in, write_addr, valid_data, data_out, ready, addr, num_enc_bytes) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """testbench for conversion purpose""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_divider(): """Wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """Dummy tests to convert the module""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = entropycoder(clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" data_in.next = 7 yield clock.posedge yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_entropycoder(): """This bench is used for conversion purpose""" # instantiate module, clock and reset inst = entropycoder(clock, reset, data_in, size, amplitude) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """dummy tests for conversion purpose""" data_in.next = 7 yield clock.posedge yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_rle_conversion(): """This bench is meant for conversion purpose""" # clock and reset signals clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # width of input data width_data = 12 # width of address bus width_addr = 6 # width to store the size width_size = width_data.bit_length() width_runlength = 4 # input data bus for rle module datastream = DataStream(width_data, width_addr) assert isinstance(datastream, DataStream) # connections between output symbols bufferdatabus = BufferDataBus(width_data, width_size, width_runlength) assert isinstance(bufferdatabus, BufferDataBus) # selects the color component, manages address values rleconfig = RLEConfig() assert isinstance(rleconfig, RLEConfig) inst = rlencoder(clock, reset, datastream, bufferdatabus, rleconfig) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """testbench for conversion purpose""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_doublebuffer_conversion(): """test bench for conversion""" clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) buffer_sel = Signal(bool(0)) width_data = 20 width_depth = 64 # instantiation of fifo-bus, clock and rledoublefifo dfifo_bus = FIFOBus(width=width_data) inst = doublefifo( clock, reset, dfifo_bus, buffer_sel, depth=width_depth) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """some tests for conversion purpose""" # select first buffer buffer_sel.next = False yield clock.posedge # write first data into double buffer dfifo_bus.write.next = True # convert signed number to unsigned dfifo_bus.write_data.next = 3 yield clock.posedge dfifo_bus.write.next = False yield clock.posedge assert dfifo_bus.empty yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_doublebuffer_conversion(): """ test bench """ clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) width = 20 dfifo_bus = DoubleFifoBus(width=width) inst = doublefifo(clock, reset, dfifo_bus, width=width, depth=64) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_color_trans(): tbdut = rgb2ycbcr_v2(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): for j in range(3): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] rgb.color_mode.next = j yield clock.posedge @instance def monitor(): samples_count = 0 yield ycbcr.data_valid.posedge yield delay(1) while samples_count != samples: for i in range(3): if i == 0: print_sig.next = exp_y[samples_count] elif i == 1: print_sig.next = exp_cb[samples_count] else: print_sig.next = exp_cr[samples_count] yield delay(1) print("%d %d" % (ycbcr.data_out, print_sig)) yield clock.posedge samples_count += 1 raise StopSimulation return tbdut, tbclk, tbstim, monitor, tbrst