def read_block(output_data_bus, clock):
"""This function reads the data from FIFO"""
assert isinstance(output_data_bus, HuffBufferDataBus)
# enable read signal
yield toggle_signal(output_data_bus.read_req, clock)
print ("%s" % bin(output_data_bus.huf_packed_byte))
# read all the data from FIFO
while not output_data_bus.fifo_empty:
yield toggle_signal(output_data_bus.read_req, clock)
print ("%s" % bin(output_data_bus.huf_packed_byte))
def read_block(output_data_bus, clock):
"""This function reads the data from FIFO"""
assert isinstance(output_data_bus, HuffBufferDataBus)
# enable read signal
yield toggle_signal(output_data_bus.read_req, clock)
print("%s" % bin(output_data_bus.huf_packed_byte))
# read all the data from FIFO
while not output_data_bus.fifo_empty:
yield toggle_signal(output_data_bus.read_req, clock)
print("%s" % bin(output_data_bus.huf_packed_byte))
def tbstim():
"""stimulus generates inputs for byte stuffer"""
# reset the module
yield pulse_reset(reset, clock)
yield toggle_signal(bs_cntrl.start, clock)
yield clock.posedge
# send input data
for i in range(64):
# send 0xFF bytes
if i % 5 == 0:
bs_in_stream.data_in.next = 0xFF
# send other bytes
else:
bs_in_stream.data_in.next = i
yield clock.posedge
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
# assert fifo empty when all the inputs are over
if i == 63:
bs_in_stream.fifo_empty.next = True
for _ in range(3):
yield clock.posedge
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
yield toggle_signal(bs_cntrl.sof, clock)
# if last byte is 0xFF. Print the zero's stuffed
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
print("total encoded bytes is %d" % num_enc_bytes)
raise StopSimulation
def tbstim():
"""stimulus generates inputs for byte stuffer"""
# reset the module
yield pulse_reset(reset, clock)
yield toggle_signal(bs_cntrl.start, clock)
yield clock.posedge
# send input data
for i in range(64):
# send 0xFF bytes
if i % 5 == 0:
bs_in_stream.data_in.next = 0xFF
# send other bytes
else:
bs_in_stream.data_in.next = i
yield clock.posedge
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
# assert fifo empty when all the inputs are over
if i == 63:
bs_in_stream.fifo_empty.next = True
for _ in range(3):
yield clock.posedge
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
yield toggle_signal(bs_cntrl.sof, clock)
# if last byte is 0xFF. Print the zero's stuffed
if bs_out_stream.data_valid:
print("output data is %d" % bs_out_stream.byte)
print("total encoded bytes is %d" % num_enc_bytes)
raise StopSimulation
def quant_top_block_process(
clock, control_unit, color, output_interface,
input_interface, input_val, rom, max_addr, buffer_sel):
"""Processing the block of pixels here"""
assert isinstance(input_interface, QuantIODataStream)
assert isinstance(output_interface, QuantIODataStream)
assert isinstance(control_unit, QuantCtrl)
# select which component to be processes
control_unit.color_component.next = color
yield clock.posedge
# select the table for quantization
if control_unit.color_component < 2:
table = 0
else:
table = 1
# calculate the reference values for the input
list_ouput_ref = []
for i in range(max_addr):
result = divider_ref(input_val[i], rom[i + (max_addr*table)])
list_ouput_ref.append(int(result))
# start processing of block
yield toggle_signal(control_unit.start, clock)
# send 64 inputs into the module
# store 64 inputs into the buffer
for i in range(max_addr):
input_interface.data.next = input_val[i]
input_interface.addr.next = buffer_sel*64 + i
yield clock.posedge
# output data from the buffer and print them
for i in range(max_addr):
output_interface.addr.next = i
if i >= 2:
print (" output data is %d" % (output_interface.data))
#assert list_ouput_ref.pop(0) == output_interface.data
yield clock.posedge
# print left outputs
print (" output data is %d" % (output_interface.data))
#assert list_ouput_ref.pop(0) == output_interface.data
yield clock.posedge
# print left outputs
print (" output data is %d" % (output_interface.data))
def quant_top_block_process(clock, control_unit, color, output_interface,
input_interface, input_val, rom, max_addr,
buffer_sel):
"""Processing the block of pixels here"""
assert isinstance(input_interface, QuantIODataStream)
assert isinstance(output_interface, QuantIODataStream)
assert isinstance(control_unit, QuantCtrl)
# select which component to be processes
control_unit.color_component.next = color
yield clock.posedge
# select the table for quantization
if control_unit.color_component < 2:
table = 0
else:
table = 1
# calculate the reference values for the input
list_ouput_ref = []
for i in range(max_addr):
result = divider_ref(input_val[i], rom[i + (max_addr * table)])
list_ouput_ref.append(int(result))
# start processing of block
yield toggle_signal(control_unit.start, clock)
# send 64 inputs into the module
# store 64 inputs into the buffer
for i in range(max_addr):
input_interface.data.next = input_val[i]
input_interface.addr.next = buffer_sel * 64 + i
yield clock.posedge
# output data from the buffer and print them
for i in range(max_addr):
output_interface.addr.next = i
if i >= 2:
print(" output data is %d" % (output_interface.data))
#assert list_ouput_ref.pop(0) == output_interface.data
yield clock.posedge
# print left outputs
print(" output data is %d" % (output_interface.data))
#assert list_ouput_ref.pop(0) == output_interface.data
yield clock.posedge
# print left outputs
print(" output data is %d" % (output_interface.data))
def tbstim():
"""Huffman input tests given here"""
# reset the stimulus before sending data in
yield pulse_reset(reset, clock)
bufferdatabus.buffer_sel.next = False
# send y1 component into the module
color = component.y1_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_y, runlength_test_y,
vli_size_test_y, clock)
print ("=======================================")
# read y1 component from the double FIFO
bufferdatabus.buffer_sel.next = True
yield read_block(bufferdatabus, clock)
print ("==============================")
# send cb component into the module
color = component.cb_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_cb, runlength_test_cb,
vli_size_test_cb, clock)
print ("==========================================")
# read cb component from the double FIFO
bufferdatabus.buffer_sel.next = False
yield clock.posedge
yield read_block(bufferdatabus, clock)
print ("==============================")
# send cr component into the module
color = component.cr_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_cr, runlength_test_cr,
vli_size_test_cr, clock)
print ("============================")
# read cr component from the double FIFO
bufferdatabus.buffer_sel.next = True
yield clock.posedge
yield read_block(bufferdatabus, clock)
print ("==============================")
yield toggle_signal(huffmancntrl.sof, clock)
raise StopSimulation
def tbstim():
"""Huffman input tests given here"""
# reset the stimulus before sending data in
yield pulse_reset(reset, clock)
bufferdatabus.buffer_sel.next = False
# send y1 component into the module
color = component.y1_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_y, runlength_test_y,
vli_size_test_y, clock)
print("=======================================")
# read y1 component from the double FIFO
bufferdatabus.buffer_sel.next = True
yield read_block(bufferdatabus, clock)
print("==============================")
# send cb component into the module
color = component.cb_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_cb, runlength_test_cb,
vli_size_test_cb, clock)
print("==========================================")
# read cb component from the double FIFO
bufferdatabus.buffer_sel.next = False
yield clock.posedge
yield read_block(bufferdatabus, clock)
print("==============================")
# send cr component into the module
color = component.cr_space
yield write_block(huffmandatastream, huffmancntrl, rle_fifo_empty,
color, vli_test_cr, runlength_test_cr,
vli_size_test_cr, clock)
print("============================")
# read cr component from the double FIFO
bufferdatabus.buffer_sel.next = True
yield clock.posedge
yield read_block(bufferdatabus, clock)
print("==============================")
yield toggle_signal(huffmancntrl.sof, clock)
raise StopSimulation
def write_block(clock, block, datastream, rleconfig, color):
"""Write the data into RLE Double Buffer"""
# select one among Y1,Y2 or Cb or Cr to be processes
rleconfig.color_component.next = color
# wait till start signal asserts
yield toggle_signal(datastream.start, clock)
# read data into rle module
datastream.input_val.next = block[rleconfig.read_addr]
yield clock.posedge
while rleconfig.read_addr != 63:
# more reads
datastream.input_val.next = block[rleconfig.read_addr]
yield clock.posedge
datastream.input_val.next = block[rleconfig.read_addr]
# wait till all the inputs are written into RLE Double Fifo
for _ in range(4):
yield clock.posedge
def write_block(
clock, block_in, input_interface, control_unit, color):
"""Write the data into RLE Double Buffer"""
max_cnt = 2**(len(input_interface.read_addr)) - 1
# select one among y1,y2 or cb or cr to be processes
control_unit.color_component.next = color
# wait till start signal asserts
yield toggle_signal(control_unit.start, clock)
# read data into rle module
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
while input_interface.read_addr != max_cnt:
# more reads
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
input_interface.data_in.next = block_in[input_interface.read_addr]
# wait till all the inputs are written into RLE Double Fifo
for _ in range(4):
yield clock.posedge
def write_block(
clock, block_in, input_interface, control_unit, color):
"""Write the data into RLE Double Buffer"""
max_cnt = 2**(len(input_interface.read_addr)) - 1
# select one among y1,y2 or cb or cr to be processes
control_unit.color_component.next = color
# wait till start signal asserts
yield toggle_signal(control_unit.start, clock)
# read data into rle module
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
while input_interface.read_addr != max_cnt:
# more reads
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
input_interface.data_in.next = block_in[input_interface.read_addr]
# wait till all the inputs are written into RLE Double Fifo
for _ in range(4):
yield clock.posedge
def block_process(
clock, block_in, input_interface,
output_interface, control_unit, color, max_count):
"""
This block sends data into rlecore and prints the output
block_in : input data block
input_interface : datastream bus interface
output_interface : bufferdata bus interface
control_unit : rleconfig interface
max_count : depth of fifo
color : color component to be processes
"""
assert isinstance(input_interface, DataStream)
assert isinstance(output_interface, RLESymbols)
assert isinstance(control_unit, RLEConfig)
# select one among y1,y2, cb or cr
control_unit.color_component.next = color
# wait till start signal asserts
yield toggle_signal(control_unit.start, clock)
# read input from the block
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
# read more inputs
while input_interface.read_addr != max_count:
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
# print output
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
# extra clocks for all the inputs to process
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
def tbstim():
"""stimulus generates inputs for entropy coder"""
# reset the module
output_model = [0] * 64
yield pulse_reset(reset, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
write_addr.next = 64
for i in range(64):
data_in.next = i % 25
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
for _ in range(35):
yield clock.posedge
# start the blocks
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 16
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 47
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 28
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 40
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 31
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
print("===================")
for i in range(addr):
print("outputs_hdl %d" % output_model[i])
print("======================")
# get outputs from reference values
output_ref = []
output_ref = backend_soft()
for i in range(len(output_ref)):
print("outputs_soft %d" % int(output_ref[i], 2))
print("===========================")
# compare reference and HDL outputs
for i in range(len(output_ref)):
assert int(output_ref[i], 2) == output_model[i]
raise StopSimulation
def tbstim():
"""stimulus generates inputs for entropy coder"""
# reset the module
output_model = [0]*64
yield pulse_reset(reset, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
write_addr.next = 64
for i in range(64):
data_in.next = i % 25
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
for _ in range(35):
yield clock.posedge
# start the blocks
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 16
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 47
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 28
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 40
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 31
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
print ("===================")
for i in range(addr):
print ("outputs_hdl %d" % output_model[i])
print ("======================")
# get outputs from reference values
output_ref = []
output_ref = backend_soft()
for i in range(len(output_ref)):
print ("outputs_soft %d" % int(output_ref[i], 2))
print ("===========================")
# compare reference and HDL outputs
for i in range(len(output_ref)):
assert int(output_ref[i], 2) == output_model[i]
raise StopSimulation
def block_process(
clock, block_in, input_interface,
output_interface, control_unit, color, max_count):
"""
This block sends data into rlecore and prints the output
block_in : input data block
input_interface : datastream bus interface
output_interface : bufferdata bus interface
control_unit : rleconfig interface
max_count : depth of fifo
color : color component to be processes
"""
assert isinstance(input_interface, DataStream)
assert isinstance(output_interface, RLESymbols)
assert isinstance(control_unit, RLEConfig)
# select one among y1,y2, cb or cr
control_unit.color_component.next = color
# wait till start signal asserts
yield toggle_signal(control_unit.start, clock)
# read input from the block
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
# read more inputs
while input_interface.read_addr != max_count:
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
# print output
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
input_interface.data_in.next = block_in[input_interface.read_addr]
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
# extra clocks for all the inputs to process
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
yield clock.posedge
if output_interface.dovalid:
print("amplitude = %d runlength = %d size = %d" % (
output_interface.amplitude,
output_interface.runlength, output_interface.size))
