def setUp(self):
bitwidth = 32
self.bytewidth = bitwidth//8
self.clock = Signal(False)
self.reset = Signal(False)
self.axis_source = AxiStreamInterface(self.bytewidth, use_TLAST=True)
self.axis_sink = AxiStreamInterface(self.bytewidth, use_TLAST=True)
self.test_count = 0
self.tests_run = False
self.args = {
'clock': self.clock,
'reset': self.reset,
'axis_source': self.axis_source,
'axis_sink': self.axis_sink,}
self.axis_source_types = (
axis_types_generator(sink=False, use_TLAST=True))
self.axis_sink_types = (
axis_types_generator(sink=True, use_TLAST=True))
self.arg_types = {
'clock': 'clock',
'reset': 'custom',
'axis_source': self.axis_source_types,
'axis_sink': self.axis_sink_types,}
def setUp(self):
self.clock = Signal(False)
self.enable = Signal(True)
self.axis_in = AxiStreamInterface(4, use_TLAST=False)
self.axis_out = AxiStreamInterface(4, use_TLAST=False)
axis_in_signal_types = {
'TDATA': 'random',
'TVALID': 'random',
'TREADY': 'output'
}
axis_out_signal_types = {
'TDATA': 'output',
'TVALID': 'output',
'TREADY': 'random'
}
self.default_args = {
'clock': self.clock,
'enable': self.enable,
'axis_in': self.axis_in,
'axis_out': self.axis_out
}
self.default_arg_types = {
'clock': 'clock',
'enable': 'custom',
'axis_in': axis_in_signal_types,
'axis_out': axis_out_signal_types
}
def setUp(self):
self.clock = Signal(False)
self.reset = Signal(False)
self.axis_in = AxiStreamInterface(4, use_TLAST=True)
self.axis_out = AxiStreamInterface(4, use_TLAST=True)
self.go = Signal(False)
self.default_args = {
'clock': self.clock,
'reset': self.reset,
'axis_in': self.axis_in,
'axis_out': self.axis_out,
'go': self.go
}
def setUp(self):
self.clock = Signal(False)
self.reset = Signal(False)
self.axis_in = AxiStreamInterface(4, use_TLAST=True)
self.axis_out = AxiStreamInterface(4, use_TLAST=True)
self.period = Signal(intbv(1, min=1, max=10))
self.default_args = {
'clock': self.clock,
'reset': self.reset,
'axis_in': self.axis_in,
'axis_out': self.axis_out,
'period': self.period
}
def setUp(self):
bitwidth = 32
self.bytewidth = bitwidth//8
self.clock = Signal(False)
self.reset = Signal(False)
self.axis_source = AxiStreamInterface(self.bytewidth, use_TLAST=True)
self.axis_sink = AxiStreamInterface(self.bytewidth, use_TLAST=True)
self.args = {
'clock': self.clock,
'reset': self.reset,
'axis_source': self.axis_source,
'axis_sink': self.axis_sink,}
def test_tkeep_rejection(self):
''' The `axis_buffer` should raise a ValueError if the AXI stream
interfaces include TKEEP.
'''
self.args['axis_source'] = (
AxiStreamInterface(self.bytewidth, use_TKEEP=True))
self.args['axis_sink'] = (
AxiStreamInterface(self.bytewidth, use_TKEEP=True))
self.assertRaisesRegex(
ValueError,
'The axis_buffer does not support TKEEP.',
axis_buffer,
**self.args)
def setUp(self):
self.clock = Signal(False)
self.reset = Signal(False)
self.axis_interface = AxiStreamInterface(4, use_TLAST=False)
self.count = Signal(intbv(0)[32:])
# With in TVALID and out TREADY set to random, about 25% of the
# time we will have a transaction
# We make TDATA an output because it is not used so we can just
# driver it low
axis_interface_signal_types = {
'TDATA': 'custom',
'TVALID': 'random',
'TREADY': 'random'
}
self.default_args = {
'clock': self.clock,
'reset': self.reset,
'axis_interface': self.axis_interface,
'count': self.count
}
self.default_arg_types = {
'clock': 'clock',
'reset': 'custom',
'axis_interface': axis_interface_signal_types,
'count': 'output'
}
def test_tuser_rejection(self):
''' The `axis_buffer` should raise a ValueError if the AXI stream
interfaces include TUSER.
'''
tuser_width = random.randrange(1, 10)
self.args['axis_source'] = (
AxiStreamInterface(self.bytewidth, TUSER_width=tuser_width))
self.args['axis_sink'] = (
AxiStreamInterface(self.bytewidth, TUSER_width=tuser_width))
self.assertRaisesRegex(
ValueError,
'The axis_buffer does not support TUSER.',
axis_buffer,
**self.args)
def test_no_tlast(self):
''' The `axis_buffer` should function correctly even when the AXI
stream interfaces don't include a `TLAST` signal.
'''
if not self.testing_using_vivado:
cycles = 30000
max_n_samples = 256
n_tests = 20
else:
cycles = 4000
max_n_samples = 25
n_tests = 10
self.args['axis_source'] = (
AxiStreamInterface(self.bytewidth, use_TLAST=False))
self.args['axis_sink'] = (
AxiStreamInterface(self.bytewidth, use_TLAST=False))
self.arg_types['axis_source'] = (
axis_types_generator(sink=False, use_TLAST=False))
self.arg_types['axis_sink'] = (
axis_types_generator(sink=True, use_TLAST=False))
@block
def test(clock, reset, axis_source, axis_sink):
return_objects = []
return_objects.append(
self.axis_buffer_check(
clock, reset, axis_source, axis_sink,
max_n_samples=max_n_samples,
randomise_axis_control_signals=True))
return_objects.append(self.count_tests(clock, n_tests))
return return_objects
dut_outputs, ref_outputs = self.cosimulate(
cycles, axis_buffer, axis_buffer, self.args, self.arg_types,
custom_sources=[(test, (), self.args)])
self.assertTrue(self.tests_run)
self.assertTrue(dut_outputs == ref_outputs)
def setUp(self):
self.clock = Signal(False)
self.reset = Signal(False)
self.axis_in = AxiStreamInterface(4, use_TLAST=True)
self.axis_out = AxiStreamInterface(4, use_TLAST=True)
self.stream = (0, 0)
# Give self.period an initial value of something typical
self.period = Signal(intbv(11, min=1, max=20))
self.default_args = {
'clock': self.clock,
'reset': self.reset,
'axis_in': self.axis_in,
'axis_out': self.axis_out,
'period': self.period
}
axis_in_signal_types = {
'TDATA': 'custom',
'TVALID': 'custom',
'TREADY': 'output',
'TLAST': 'custom'
}
axis_out_signal_types = {
'TDATA': 'output',
'TVALID': 'output',
'TREADY': 'custom',
'TLAST': 'output'
}
self.default_arg_types = {
'clock': 'clock',
'reset': 'custom',
'axis_in': axis_in_signal_types,
'axis_out': axis_out_signal_types,
'period': 'custom'
}
self.test_data = {'enable_count': 0}
def test_axis_out_has_TLAST(self):
'''The axis_out port should have the TLAST signal.
If it does not, a ValueError should be raised.
'''
args = self.default_args.copy()
args['axis_out'] = AxiStreamInterface(4, use_TLAST=False)
self.assertRaisesRegex(ValueError, 'Missing axis_out TLAST signal',
axis_packet_gate, **args)
def setUp(self):
self.clock = Signal(False)
self.reset = Signal(False)
self.axis_interface = AxiStreamInterface(4, use_TLAST=False)
self.count = Signal(intbv(0)[32:])
self.default_args = {
'clock': self.clock,
'reset': self.reset,
'axis_interface': self.axis_interface,
'count': self.count
}
def setUp(self):
self.clock = Signal(False)
self.reset = Signal(False)
self.axis_in = AxiStreamInterface(4, use_TLAST=True)
self.axis_out = AxiStreamInterface(4, use_TLAST=True)
self.go = Signal(False)
self.default_args = {
'clock': self.clock,
'reset': self.reset,
'axis_in': self.axis_in,
'axis_out': self.axis_out,
'go': self.go
}
axis_in_signal_types = {
'TDATA': 'custom',
'TVALID': 'custom',
'TREADY': 'output',
'TLAST': 'custom'
}
axis_out_signal_types = {
'TDATA': 'output',
'TVALID': 'output',
'TREADY': 'custom',
'TLAST': 'output'
}
self.default_arg_types = {
'clock': 'clock',
'reset': 'custom',
'axis_in': axis_in_signal_types,
'axis_out': axis_out_signal_types,
'go': 'custom'
}
def test_missing_TLASTs(self):
'''If neither ``axis_in`` not ``axis_out`` have a TLAST, then the
block should still work just without any TLAST signals.
'''
# We should never reach this number of cycles as we can raise
# StopSimulation once we've completed the tests
max_cycles = 20000
self.axis_in = AxiStreamInterface(4, use_TLAST=False)
self.axis_out = AxiStreamInterface(4, use_TLAST=False)
self.default_args['axis_in'] = self.axis_in
del self.default_arg_types['axis_in']['TLAST']
self.default_args['axis_out'] = self.axis_out
del self.default_arg_types['axis_out']['TLAST']
self.period = random.randrange(2, 20)
axis_write_bfm = AxiStreamMasterBFM()
axis_read_bfm = AxiStreamSlaveBFM()
max_packet_len = 100
min_packet_len = 50
max_input_val = self.axis_in.TDATA.max
# Randomly determine the number of packets to write
n_packets = random.randrange(5, 10)
# TID and TDEST are not used therefore the stream value will be
# interpreted as zeroes by the AxiSlaceBFM
stream = self.stream
write_data = {stream: deque([])}
for x in range(n_packets):
packet = deque([
random.randrange(0, max_input_val) for x in range(
random.randrange(min_packet_len, max_packet_len))
])
write_data[stream].append(packet)
n_samples = sum(len(packet) for packet in write_data[stream])
axis_write_bfm.add_data(write_data[stream])
self.default_args['period'] = self.period
self.default_arg_types['period'] = 'non-signal'
checker_args = self.default_args.copy()
checker_args['read_bfm'] = axis_read_bfm
checker_args['write_bfm'] = axis_write_bfm
checker_args['n_expected_output_packets'] = len(write_data[stream])
dut_outputs, ref_outputs = self.cosimulate(max_cycles,
axis_periodic_enable,
axis_periodic_enable,
self.default_args,
self.default_arg_types,
custom_sources=[
(self.checker, (),
checker_args)
])
# Flatten the packet
expected_output = {}
expected_output[stream] = deque(
[item for packet in write_data[stream] for item in packet])
self.assertTrue(axis_read_bfm.current_packets == expected_output)
self.assertTrue(dut_outputs == ref_outputs)
def test_no_output_TLAST(self):
'''If the ``axis_out`` does not have a TLAST, then the input TLAST
is simply ignored.
'''
# We should never reach this number of cycles as we can raise
# StopSimulation once we've completed the tests
max_cycles = 20000
self.axis_out = AxiStreamInterface(4, use_TLAST=False)
self.default_args['axis_out'] = self.axis_out
del self.default_arg_types['axis_out']['TLAST']
self.period = random.randrange(2, 20)
axis_write_bfm = AxiStreamMasterBFM()
axis_read_bfm = AxiStreamSlaveBFM()
max_packet_len = 100
min_packet_len = 50
max_input_val = self.axis_in.TDATA.max
# Randomly determine the number of packets to write
n_packets = random.randrange(5, 10)
# TID and TDEST are not used therefore the stream value will be
# interpreted and zeroes by the AxiSlaceBFM
stream = self.stream
write_data = {stream: deque([])}
for x in range(n_packets):
packet = deque([
random.randrange(0, max_input_val) for x in range(
random.randrange(min_packet_len, max_packet_len))
])
write_data[stream].append(packet)
n_samples = sum(len(packet) for packet in write_data[stream])
axis_write_bfm.add_data(write_data[stream])
self.default_args['period'] = self.period
self.default_arg_types['period'] = 'non-signal'
checker_args = self.default_args.copy()
checker_args['read_bfm'] = axis_read_bfm
checker_args['write_bfm'] = axis_write_bfm
checker_args['n_expected_output_packets'] = len(write_data[stream])
with warnings.catch_warnings():
warnings.filterwarnings(
'ignore',
message='Signal is driven but not read: axis_in_TLAST',
category=myhdl.ToVHDLWarning)
warnings.filterwarnings(
'ignore',
message='Signal is driven but not read: axis_in_TLAST',
category=myhdl.ToVerilogWarning)
dut_outputs, ref_outputs = self.cosimulate(max_cycles,
axis_periodic_enable,
axis_periodic_enable,
self.default_args,
self.default_arg_types,
custom_sources=[
(self.checker, (),
checker_args)
])
# Flatten the packet
expected_output = {}
expected_output[stream] = deque(
[item for packet in write_data[stream] for item in packet])
self.assertTrue(axis_read_bfm.current_packets == expected_output)
self.assertTrue(dut_outputs == ref_outputs)