def sram_ctrl_logic(self):
if ~self.WEB:
self.web_demux = ~(const(1, width=self.num_sram_macros) << resize(
self.sram_sel, self.num_sram_macros))
else:
self.web_demux = const(2**self.num_sram_macros - 1,
self.num_sram_macros)
if ~self.CEB:
self.ceb_demux = ~(const(1, width=self.num_sram_macros) << resize(
self.sram_sel, self.num_sram_macros))
else:
self.ceb_demux = const(2**self.num_sram_macros - 1,
self.num_sram_macros)
def test_resize():
from kratos import resize
mod = Generator("mod")
a = mod.var("a", 1)
b = resize(a, 16)
assert b.width == 16
assert str(b) == "16'(a)"
def pipeline(self):
if self.reset:
for i in range(self.depth):
if self.reset_high:
self.pipeline_r[i] = const(2**self.width - 1, self.width)
else:
self.pipeline_r[i] = 0
elif self.clk_en:
for i in range(self.depth):
if i == 0:
self.pipeline_r[i] = self.in_
else:
self.pipeline_r[i] = self.pipeline_r[resize(
i - 1, self.depth_width)]
def add_done_pulse_pipeline(self):
maximum_latency = 2 * self._params.num_glb_tiles + self.default_latency
latency_width = clog2(maximum_latency)
self.done_pulse_d_arr = self.var(
"done_pulse_d_arr", 1, size=maximum_latency, explicit_array=True)
self.done_pulse_pipeline = Pipeline(width=1,
depth=maximum_latency,
flatten_output=True)
self.add_child("done_pulse_pipeline",
self.done_pulse_pipeline,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
in_=self.done_pulse_w,
out_=self.done_pulse_d_arr)
self.wire(self.st_dma_done_pulse,
self.done_pulse_d_arr[resize(self.cfg_data_network_latency, latency_width) + self.default_latency])
def mem_ff(self):
if self.CEB == 0:
self.Q_w = concat(
self.mem[resize((self.A << 2) + 3, self.addr_width + 2)],
self.mem[resize((self.A << 2) + 2, self.addr_width + 2)],
self.mem[resize((self.A << 2) + 1,
self.addr_width + 2)], self.mem[resize(
(self.A << 2), self.addr_width + 2)])
if self.WEB == 0:
for i in range(self.data_width):
if self.BWEB[i] == 0:
self.mem[resize(
(self.A << 2) + i // 16,
self.addr_width + 2)][resize(
i % 16, clog2(
self._params.cgra_data_width))] = self.D[i]
def add_strm_rd_addr_pipeline(self):
maximum_latency = 2 * self._params.num_glb_tiles + self.default_latency
latency_width = clog2(maximum_latency)
self.strm_rd_addr_d_arr = self.var("strm_rd_addr_d_arr",
width=self._params.glb_addr_width,
size=maximum_latency,
explicit_array=True)
self.strm_rd_addr_pipeline = Pipeline(
width=self._params.glb_addr_width,
depth=maximum_latency,
flatten_output=True)
self.add_child("strm_rd_addr_pipeline",
self.strm_rd_addr_pipeline,
clk=self.clk,
clk_en=self.clk_en,
reset=self.reset,
in_=self.strm_rd_addr_w,
out_=self.strm_rd_addr_d_arr)
self.strm_data_sel = self.strm_rd_addr_d_arr[
resize(self.cfg_data_network_latency, latency_width) +
self.default_latency][self._params.bank_byte_offset - 1,
self._params.cgra_byte_offset]
def strm_rdrq_packet_ff(self):
self.strm_rd_en_w = self.cycle_valid
self.strm_rd_addr_w = resize(self.data_current_addr,
self._params.glb_addr_width)
def strm_wr_packet_comb(self):
self.strm_wr_en_w = self.cycle_valid_muxed
self.strm_wr_addr_w = resize(self.data_current_addr, self._params.glb_addr_width)
self.strm_wr_data_w = self.data_f2g