def test_conf():
c = Configuration_Lightpix_v1()
endian = 'little'
# test simple register
c.timeout = 12
assert c.timeout == 12
assert c.timeout_data == [(238, bah.fromuint(12,8, endian=endian))]
c.timeout_data = (238, bah.fromuint(90,8, endian=endian))
assert c.timeout == 90
assert c.timeout_data == [(238, bah.fromuint(90,8, endian=endian))]
c.timeout_data = bah.fromuint(34,8, endian=endian)
assert c.timeout == 34
assert c.timeout_data == [(238, bah.fromuint(34,8, endian=endian))]
# test compound register
c.lightpix_mode = 1
c.hit_threshold = 3
reg_data = [(237, bitarray('11100000'))]
assert c.lightpix_mode == 1
assert c.lightpix_mode_data == reg_data
assert c.hit_threshold == 3
assert c.hit_threshold_data == reg_data
c.hit_threshold = 0
reg_data = [(237, bitarray('10000000'))]
assert c.lightpix_mode == 1
assert c.lightpix_mode_data == reg_data
assert c.hit_threshold == 0
assert c.hit_threshold_data == reg_data
def set_utility_pulse(self, pulse_len=None, pulse_rep=None):
'''
Sends a special command to issue set up utility pulser. Pulse length
is the number of larpix clk cyles pulse is high, and pulse rep is the
number of clk cycles until the next pulse.
'''
data_out = b''
if not pulse_len is None:
data_out += (
b'c' # start byte
+ b'\x03' # address
+ bah.fromuint(max(pulse_len-2,0), 32, endian='big').tobytes()[::-1] # -2 for proper register value -> clk cycles conv.
+ b'\x00'*3 # unused
+ b'q' # stop byte
)
if not pulse_rep is None:
data_out += (
b'c' # start byte
+ b'\x04' # address
+ bah.fromuint(max(pulse_rep-1,0), 32, endian='big').tobytes()[::-1] # -1 for proper register value -> clk cycles conv.
+ b'\x00'*3 # unused
+ b'q' # stop byte
)
if data_out:
self._write(data_out)
else:
raise RuntimeError('set either or both of pulse_len and pulse_rep')
def set_larpix_reset_cnt(self, value):
'''
Sends a special command to modify the length of the reset signal
sent to the larpix chips. The reset will be held low for value + 1
larpix clk rising edges
'''
data_out = (
b'c' # start byte
+ b'\x01' # address
+ bah.fromuint(value, 8, endian='big').tobytes()
+ b'\x00'*6 # unused
+ b'q' # stop byte
)
self._write(data_out)
def set_larpix_uart_clk_ratio(self, value):
'''
Sends a special command to modify the larpix uart clk ratio (how many
clock cycles correspond to one bit). A value of 2 means 1 uart bit == 2
clk cycles
'''
data_out = (
b'c' # start byte
+ b'\x00' # address
+ bah.fromuint(value, 8, endian='big').tobytes()
+ b'\x00'*6 # unused
+ b'q' # stop byte
)
self._write(data_out)
def test_conf():
c = Configuration_v2()
endian = 'little'
# test simple register
c.threshold_global = 255
assert c.threshold_global == 255
assert c.threshold_global_data == [(64, bah.fromuint(255, 8,
endian=endian))]
c.threshold_global_data = (64, bah.fromuint(253, 8, endian=endian))
assert c.threshold_global == 253
assert c.threshold_global_data == [(64, bah.fromuint(253, 8,
endian=endian))]
c.threshold_global_data = bah.fromuint(252, 8, endian=endian)
assert c.threshold_global == 252
assert c.threshold_global_data == [(64, bah.fromuint(252, 8,
endian=endian))]
# test list register
c.pixel_trim_dac = [0] * 64
assert c.pixel_trim_dac == [0] * 64
assert c.pixel_trim_dac_data == [(i, bah.fromuint(0, 8, endian=endian))
for i in range(64)]
c.pixel_trim_dac[1] = 1
assert c.pixel_trim_dac[1] == 1
assert c.pixel_trim_dac_data[1] == (1, bah.fromuint(1, 8, endian=endian))
assert c.pixel_trim_dac_data[0] == (0, bah.fromuint(0, 8, endian=endian))
c.pixel_trim_dac_data = (1, bah.fromuint(2, 8, endian=endian))
assert c.pixel_trim_dac[1] == 2
assert c.pixel_trim_dac_data[1] == (1, bah.fromuint(2, 8, endian=endian))
assert c.pixel_trim_dac_data[0] == (0, bah.fromuint(0, 8, endian=endian))
bits = bitarray()
for i in range(64):
bits += bah.fromuint(31, 8, endian=endian)
c.pixel_trim_dac_data = bits
assert c.pixel_trim_dac[1] == 31
assert c.pixel_trim_dac[0] == 31
assert c.pixel_trim_dac_data[1] == (1, bah.fromuint(31, 8, endian=endian))
assert c.pixel_trim_dac_data[0] == (0, bah.fromuint(31, 8, endian=endian))
# test compound register
c.csa_gain = 1
c.csa_bypass_enable = 1
c.bypass_caps_en = 1
reg_data = [(65, bitarray('11100000'))]
assert c.csa_gain == 1
assert c.csa_gain_data == reg_data
assert c.csa_bypass_enable == 1
assert c.csa_bypass_enable_data == reg_data
assert c.bypass_caps_en == 1
assert c.bypass_caps_en_data == reg_data
c.csa_bypass_enable = 0
reg_data = [(65, bitarray('10100000'))]
assert c.csa_gain == 1
assert c.csa_gain_data == reg_data
assert c.csa_bypass_enable == 0
assert c.csa_bypass_enable_data == reg_data
assert c.bypass_caps_en == 1
assert c.bypass_caps_en_data == reg_data
reg_data = [(65, bitarray('01000000'))]
c.csa_bypass_enable_data = reg_data[0]
assert c.csa_gain == 0
assert c.csa_gain_data == reg_data
assert c.csa_bypass_enable == 1
assert c.csa_bypass_enable_data == reg_data
assert c.bypass_caps_en == 0
assert c.bypass_caps_en_data == reg_data
reg_data = [(65, bitarray('11000000'))]
c.csa_gain_data = bitarray('1')
assert c.csa_gain == 1
assert c.csa_gain_data == reg_data
assert c.csa_bypass_enable == 1
assert c.csa_bypass_enable_data == reg_data
assert c.bypass_caps_en == 0
assert c.bypass_caps_en_data == reg_data
# test list register (that covers <1 register)
c.current_monitor_bank0 = [0] * 4
assert c.current_monitor_bank0 == [0] * 4
assert c.current_monitor_bank0_data == [(109,
bah.fromuint(0, 8,
endian=endian))]
c.current_monitor_bank0[1] = 1
assert c.current_monitor_bank0[1] == 1
assert c.current_monitor_bank0[0] == 0
assert c.current_monitor_bank0_data == [(109, bitarray('01000000'))]
c.current_monitor_bank0_data = (109, bitarray('00100000'))
assert c.current_monitor_bank0[1] == 0
assert c.current_monitor_bank0[2] == 1
assert c.current_monitor_bank0_data == [(109, bitarray('00100000'))]
bits = bitarray('0100')
c.current_monitor_bank0_data = bits
assert c.current_monitor_bank0[1] == 1
assert c.current_monitor_bank0[0] == 0
assert c.current_monitor_bank0_data == [(109, bitarray('01000000'))]
# test compound list register (that covers <1 register)
c.enable_miso_downstream = [0] * 4
c.enable_miso_differential = [0] * 4
assert c.enable_miso_differential == [0] * 4
assert c.enable_miso_differential_data == [(125,
bah.fromuint(0,
8,
endian=endian))]
c.enable_miso_differential[1] = 1
assert c.enable_miso_differential[1] == 1
assert c.enable_miso_differential[0] == 0
assert c.enable_miso_differential_data == [(125, bitarray('00000100'))]
c.enable_miso_differential_data = (125, bitarray('00000010'))
assert c.enable_miso_differential[1] == 0
assert c.enable_miso_differential[2] == 1
assert c.enable_miso_differential_data == [(125, bitarray('00000010'))]
bits = bitarray('0100')
c.enable_miso_differential_data = bits
assert c.enable_miso_differential[1] == 1
assert c.enable_miso_differential[0] == 0
assert c.enable_miso_differential_data == [(125, bitarray('00000100'))]
# test long register
c.periodic_trigger_cycles = 2**32 - 1
assert c.periodic_trigger_cycles == 2**32 - 1
assert c.periodic_trigger_cycles_data == [
(i, bah.fromuint(255, 8, endian=endian)) for i in range(166, 170)
]
c.periodic_trigger_cycles_data = (166, bah.fromuint(254, 8, endian=endian))
assert c.periodic_trigger_cycles == 2**32 - 2
assert c.periodic_trigger_cycles_data[0] == (166,
bah.fromuint(254,
8,
endian=endian))
c.periodic_trigger_cycles_data = bah.fromuint(1, 32, endian=endian)
assert c.periodic_trigger_cycles == 1
assert c.periodic_trigger_cycles_data[0] == (166,
bah.fromuint(1,
8,
endian=endian))
