def test_add_input_single(self): """ Test add_input with single-bit input and output components. """ in_com = ComponentBase('', 1) out_com = ComponentBase('', 0) in_com.add_input(out_com, 0) self.assertIs(out_com, in_com._input_bits[0])
def test_add_input_multicom(self): """ Test add_input with multiple devices wired to one. """ in_com = ComponentBase('', 5) out_coms = [ComponentBase('', 0), ComponentBase('', 0), ComponentBase('', 0), ComponentBase('', 0), ComponentBase('', 0)] for i in xrange(0, len(out_coms)): in_com.add_input(out_coms[i], i) for i in xrange(0, len(out_coms)): self.assertIs(out_coms[i], in_com._input_bits[i])
def test_add_input_graph(self): """ Test add_input properly puts components in children and parent lists (representing edges). """ in_com = ComponentBase('', 1, 0) out_com = ComponentBase('', 0, 1) in_com.add_input(out_com, 0) self.assertIn(out_com, in_com.parents) self.assertIn(in_com, out_com.children) self.assertEqual(1, len(in_com.parents)) self.assertEqual(1, len(out_com.children))
def test_add_input_failures(self): """ Test add_input catches invalid operations properly. """ in_com = ComponentBase('', 5) out_com1 = ComponentBase('', 0) out_com2 = ComponentBase('', 0) # Input bit out of range self.assertRaises(ValueError, in_com.add_input, out_com2, 5) self.assertRaises(ValueError, in_com.add_input, out_com2, -1) # Wiring to occupied input bit in_com.add_input(out_com1, 1) self.assertRaises(ValueError, in_com.add_input, out_com2, 1)