def test_wishbone_data_width_not_smaller(self):
with self.assertRaises(AssertionError):
wb = wishbone.Interface(data_width=32)
port = LiteDRAMNativePort("both",
address_width=32,
data_width=wb.data_width * 2)
LiteDRAMWishbone2Native(wb, port)
def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
assert not self._sdram_phy
self._sdram_phy.append(
phy) # encapsulate in list to prevent CSR scanning
self.submodules.sdram = ControllerInjector(phy, geom_settings,
timing_settings, **kwargs)
dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
sdram_width = phy.settings.dfi_databits // dfi_databits_divisor
main_ram_size = 2**(geom_settings.bankbits + geom_settings.rowbits +
geom_settings.colbits) * sdram_width // 8
# TODO: modify mem_map to allow larger memories.
main_ram_size = min(main_ram_size, 256 * 1024 * 1024)
self.add_constant("L2_SIZE", self.l2_size)
# add a Wishbone interface to the DRAM
wb_sdram = wishbone.Interface()
self.add_wb_sdram_if(wb_sdram)
self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram,
main_ram_size)
if self.l2_size:
port = self.sdram.crossbar.get_port()
self.submodules.l2_cache = wishbone.Cache(
self.l2_size // 4, self._wb_sdram,
wishbone.Interface(port.data_width))
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(
self.l2_cache.slave, port)
def __init__(self):
self.port = port
self.wb = wishbone
self.submodules += LiteDRAMWishbone2Native(
wishbone=self.wb,
port=self.port,
base_address=base_address)
self.mem = DRAMMemory(port.data_width, len(mem_expected))
def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
assert not self._sdram_phy
self._sdram_phy.append(
phy) # encapsulate in list to prevent CSR scanning
self.submodules.sdram = ControllerInjector(phy, geom_settings,
timing_settings, **kwargs)
dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
sdram_width = phy.settings.dfi_databits // dfi_databits_divisor
main_ram_size = 2**(geom_settings.bankbits + geom_settings.rowbits +
geom_settings.colbits) * sdram_width // 8
# TODO: modify mem_map to allow larger memories.
main_ram_size = min(main_ram_size, 256 * 1024 * 1024)
self.add_constant("L2_SIZE", self.l2_size)
# add a Wishbone interface to the DRAM
wb_sdram = wishbone.Interface()
self.add_wb_sdram_if(wb_sdram)
self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram,
main_ram_size)
if self.l2_size:
port = self.sdram.crossbar.get_port()
l2_cache = wishbone.Cache(self.l2_size // 4, self._wb_sdram,
wishbone.Interface(port.dw))
# XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(
self.l2_cache.slave, port)
def add_sdram(self, name, phy, module, origin, size=None,
l2_cache_size = 8192,
l2_cache_min_data_width = 128,
l2_cache_reverse = True,
l2_cache_full_memory_we = True,
**kwargs):
# LiteDRAM core ----------------------------------------------------------------------------
self.submodules.sdram = LiteDRAMCore(
phy = phy,
geom_settings = module.geom_settings,
timing_settings = module.timing_settings,
clk_freq = self.sys_clk_freq,
**kwargs)
self.csr.add("sdram")
# LiteDRAM port ----------------------------------------------------------------------------
port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
# SDRAM size -------------------------------------------------------------------------------
sdram_size = 2**(module.geom_settings.bankbits +
module.geom_settings.rowbits +
module.geom_settings.colbits)*phy.settings.databits//8
if size is not None:
sdram_size = min(sdram_size, size)
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
# SoC [<--> L2 Cache] <--> LiteDRAM --------------------------------------------------------
if self.cpu.name == "rocket":
# Rocket has its own I/D L1 cache: connect directly to LiteDRAM when possible.
if port.data_width == self.cpu.mem_axi.data_width:
self.logger.info("Matching AXI MEM data width ({})\n".format(port.data_width))
self.submodules += LiteDRAMAXI2Native(
axi = self.cpu.mem_axi,
port = port,
base_address = self.bus.regions["main_ram"].origin)
else:
self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
port.data_width,
self.cpu.mem_axi.data_width))
# FIXME: replace WB data-width converter with native AXI converter!!!
mem_wb = wishbone.Interface(
data_width = self.cpu.mem_axi.data_width,
adr_width = 32-log2_int(self.cpu.mem_axi.data_width//8))
# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
mem_a2w = ResetInserter()(axi.AXI2Wishbone(
axi = self.cpu.mem_axi,
wishbone = mem_wb,
base_address = 0))
self.comb += mem_a2w.reset.eq(ResetSignal() | self.cpu.reset)
self.submodules += mem_a2w
litedram_wb = wishbone.Interface(port.data_width)
self.submodules += LiteDRAMWishbone2Native(
wishbone = litedram_wb,
port = port,
base_address = origin)
self.submodules += wishbone.Converter(mem_wb, litedram_wb)
elif self.with_wishbone:
# Wishbone Slave SDRAM interface -------------------------------------------------------
wb_sdram = wishbone.Interface()
self.bus.add_slave("main_ram", wb_sdram)
# L2 Cache -----------------------------------------------------------------------------
if l2_cache_size != 0:
# Insert L2 cache inbetween Wishbone bus and LiteDRAM
l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2
l2_cache_data_width = max(port.data_width, l2_cache_min_data_width)
l2_cache = wishbone.Cache(
cachesize = l2_cache_size//4,
master = wb_sdram,
slave = wishbone.Interface(l2_cache_data_width),
reverse = l2_cache_reverse)
if l2_cache_full_memory_we:
l2_cache = FullMemoryWE()(l2_cache)
self.submodules.l2_cache = l2_cache
litedram_wb = self.l2_cache.slave
else:
litedram_wb = wishbone.Interface(port.data_width)
self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
self.add_config("L2_SIZE", l2_cache_size)
# Wishbone Slave <--> LiteDRAM bridge --------------------------------------------------
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
base_address = self.bus.regions["main_ram"].origin)