def test_ddr4(self):
from litex.boards.targets.kcu105 import BaseSoC
soc = BaseSoC(max_sdram_size=0x4000000)
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True)
self.assertEqual(compare_with_reference(py_header, "ddr4_init.py"), True)
def _generate_includes(self):
cpu_type = self.soc.cpu_type
memory_regions = self.soc.get_memory_regions()
flash_boot_address = getattr(self.soc, "flash_boot_address", None)
shadow_base = getattr(self.soc, "shadow_base", None)
csr_regions = self.soc.get_csr_regions()
constants = self.soc.get_constants()
buildinc_dir = os.path.join(self.output_dir, "software", "include")
generated_dir = os.path.join(buildinc_dir, "generated")
os.makedirs(generated_dir, exist_ok=True)
if cpu_type is not None:
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(
k, _makefile_escape(v)))
for k, v in cpu_interface.get_cpu_mak(self.soc.cpu,
self.compile_software):
define(k, v)
# Distinguish between LiteX and MiSoC.
define("LITEX", "1")
# Distinguish between applications running from main RAM and
# flash for user-provided software packages.
exec_profiles = {"COPY_TO_MAIN_RAM": "0", "EXECUTE_IN_PLACE": "0"}
if "main_ram" in (m[0] for m in memory_regions):
exec_profiles["COPY_TO_MAIN_RAM"] = "1"
else:
exec_profiles["EXECUTE_IN_PLACE"] = "1"
for k, v in exec_profiles.items():
define(k, v)
define("SOC_DIRECTORY", soc_directory)
variables_contents.append("export BUILDINC_DIRECTORY\n")
define("BUILDINC_DIRECTORY", buildinc_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
write_to_file(os.path.join(generated_dir, "variables.mak"),
"".join(variables_contents))
write_to_file(os.path.join(generated_dir, "output_format.ld"),
cpu_interface.get_linker_output_format(self.soc.cpu))
write_to_file(os.path.join(generated_dir, "regions.ld"),
cpu_interface.get_linker_regions(memory_regions))
write_to_file(
os.path.join(generated_dir, "mem.h"),
cpu_interface.get_mem_header(memory_regions, flash_boot_address,
shadow_base))
write_to_file(os.path.join(generated_dir, "csr.h"),
cpu_interface.get_csr_header(csr_regions, constants))
write_to_file(os.path.join(generated_dir, "git.h"),
cpu_interface.get_git_header())
if isinstance(self.soc, soc_sdram.SoCSDRAM):
if hasattr(self.soc, "sdram"):
write_to_file(
os.path.join(generated_dir, "sdram_phy.h"),
get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing))
def test_sdr(self):
from litex.boards.targets.minispartan6 import BaseSoC
soc = BaseSoC()
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True)
self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True)
def _generate_includes(self):
os.makedirs(self.include_dir, exist_ok=True)
os.makedirs(self.generated_dir, exist_ok=True)
if self.soc.cpu_type not in [None, "zynq7000"]:
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(k, _makefile_escape(v)))
for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software):
define(k, v)
define(
"COMPILER_RT_DIRECTORY",
get_data_mod("software", "compiler_rt").data_location)
define("SOC_DIRECTORY", soc_directory)
variables_contents.append("export BUILDINC_DIRECTORY\n")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
for bios_option in self.bios_options:
assert bios_option in ["TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"]
define(bios_option, "1")
write_to_file(
os.path.join(self.generated_dir, "variables.mak"),
"".join(variables_contents))
write_to_file(
os.path.join(self.generated_dir, "output_format.ld"),
export.get_linker_output_format(self.soc.cpu))
write_to_file(
os.path.join(self.generated_dir, "regions.ld"),
export.get_linker_regions(self.soc.mem_regions))
write_to_file(
os.path.join(self.generated_dir, "mem.h"),
export.get_mem_header(self.soc.mem_regions))
write_to_file(
os.path.join(self.generated_dir, "soc.h"),
export.get_soc_header(self.soc.constants))
write_to_file(
os.path.join(self.generated_dir, "csr.h"),
export.get_csr_header(
regions = self.soc.csr_regions,
constants = self.soc.constants,
csr_base = self.soc.mem_regions['csr'].origin
)
)
write_to_file(
os.path.join(self.generated_dir, "git.h"),
export.get_git_header()
)
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"),
get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing))
def _generate_includes(self, with_bios=True):
# Generate Include/Generated directories.
_create_dir(self.include_dir)
_create_dir(self.generated_dir)
# Generate BIOS files when the SoC uses it.
if with_bios:
# Generate Variables to variables.mak.
variables_contents = self._get_variables_contents()
write_to_file(os.path.join(self.generated_dir, "variables.mak"), variables_contents)
# Generate Output Format to output_format.ld.
output_format_contents = export.get_linker_output_format(self.soc.cpu)
write_to_file(os.path.join(self.generated_dir, "output_format.ld"), output_format_contents)
# Generate Memory Regions to regions.ld.
regions_contents = export.get_linker_regions(self.soc.mem_regions)
write_to_file(os.path.join(self.generated_dir, "regions.ld"), regions_contents)
# Collect / Generate I2C config and init table.
from litex.soc.cores.bitbang import collect_i2c_info
i2c_devs, i2c_init = collect_i2c_info(self.soc)
if i2c_devs:
i2c_info = export.get_i2c_header((i2c_devs, i2c_init))
write_to_file(os.path.join(self.generated_dir, "i2c.h"), i2c_info)
# Generate Memory Regions to mem.h.
mem_contents = export.get_mem_header(self.soc.mem_regions)
write_to_file(os.path.join(self.generated_dir, "mem.h"), mem_contents)
# Generate Memory Regions to memory.x if specified.
if self.memory_x is not None:
memory_x_contents = export.get_memory_x(self.soc)
write_to_file(os.path.realpath(self.memory_x), memory_x_contents)
# Generate SoC Config/Constants to soc.h.
soc_contents = export.get_soc_header(self.soc.constants)
write_to_file(os.path.join(self.generated_dir, "soc.h"), soc_contents)
# Generate CSR registers definitions/access functions to csr.h.
csr_contents = export.get_csr_header(
regions = self.soc.csr_regions,
constants = self.soc.constants,
csr_base = self.soc.mem_regions['csr'].origin)
write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents)
# Generate Git SHA1 of tools to git.h
git_contents = export.get_git_header()
write_to_file(os.path.join(self.generated_dir, "git.h"), git_contents)
# Generate LiteDRAM C header to sdram_phy.h when the SoC use it
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
sdram_contents = get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing)
write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"), sdram_contents)
def _generate_includes(self):
os.makedirs(self.include_dir, exist_ok=True)
os.makedirs(self.generated_dir, exist_ok=True)
if self.soc.cpu_type is not None:
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(
k, _makefile_escape(v)))
for k, v in cpu_interface.get_cpu_mak(self.soc.cpu,
self.compile_software):
define(k, v)
# Distinguish between LiteX and MiSoC.
define("LITEX", "1")
# Distinguish between applications running from main RAM and
# flash for user-provided software packages.
exec_profiles = {"COPY_TO_MAIN_RAM": "0", "EXECUTE_IN_PLACE": "0"}
if "main_ram" in self.soc.mem_regions.keys():
exec_profiles["COPY_TO_MAIN_RAM"] = "1"
else:
exec_profiles["EXECUTE_IN_PLACE"] = "1"
for k, v in exec_profiles.items():
define(k, v)
define("SOC_DIRECTORY", soc_directory)
variables_contents.append("export BUILDINC_DIRECTORY\n")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
write_to_file(os.path.join(self.generated_dir, "variables.mak"),
"".join(variables_contents))
write_to_file(os.path.join(self.generated_dir, "output_format.ld"),
cpu_interface.get_linker_output_format(self.soc.cpu))
write_to_file(
os.path.join(self.generated_dir, "regions.ld"),
cpu_interface.get_linker_regions(self.soc.mem_regions))
write_to_file(os.path.join(self.generated_dir, "mem.h"),
cpu_interface.get_mem_header(self.soc.mem_regions))
write_to_file(os.path.join(self.generated_dir, "soc.h"),
cpu_interface.get_soc_header(self.soc.constants))
write_to_file(
os.path.join(self.generated_dir, "csr.h"),
cpu_interface.get_csr_header(self.soc.csr_regions,
self.soc.constants))
write_to_file(os.path.join(self.generated_dir, "git.h"),
cpu_interface.get_git_header())
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
write_to_file(
os.path.join(self.generated_dir, "sdram_phy.h"),
get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing))
def test_ddr3(self):
from litex_boards.targets.kc705 import BaseSoC
soc = BaseSoC()
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy,
soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(
soc.sdram.controller.settings.phy,
soc.sdram.controller.settings.timing)
compare_with_reference(self, c_header, "ddr3_init.h")
compare_with_reference(self, py_header, "ddr3_init.py")
def test_ddr4(self):
from litex_boards.targets.kcu105 import BaseSoC
soc = BaseSoC(max_sdram_size=0x4000000)
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy,
soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(
soc.sdram.controller.settings.phy,
soc.sdram.controller.settings.timing)
#update_c_reference(c_header, "ddr4_init.h")
compare_with_reference(self, c_header, "ddr4_init.h")
compare_with_reference(self, py_header, "ddr4_init.py")
def test_sdr(self):
from litex_boards.targets.minispartan6 import BaseSoC
soc = BaseSoC()
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy,
soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(
soc.sdram.controller.settings.phy,
soc.sdram.controller.settings.timing)
#update_c_reference(c_header, "sdr_init.h")
compare_with_reference(self, c_header, "sdr_init.h")
compare_with_reference(self, py_header, "sdr_init.py")
def _generate_includes(self):
# Generate Include/Generated directories.
_create_dir(self.include_dir)
_create_dir(self.generated_dir)
# Generate BIOS files when the SoC uses it.
with_bios = self.soc.cpu_type not in [None, "zynq7000"]
if with_bios:
# Generate Variables to variables.mak.
variables_contents = []
def define(k, v):
variables_contents.append("{}={}".format(
k, _makefile_escape(v)))
# Define the CPU variables.
for k, v in export.get_cpu_mak(self.soc.cpu,
self.compile_software):
define(k, v)
# Define the SoC/Compiler-RT/Software/Include directories.
define("SOC_DIRECTORY", soc_directory)
compiler_rt_directory = get_data_mod("software",
"compiler_rt").data_location
define("COMPILER_RT_DIRECTORY", compiler_rt_directory)
variables_contents.append("export BUILDINC_DIRECTORY")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
# Define the BIOS Options.
for bios_option in self.bios_options:
assert bios_option in [
"TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"
]
define(bios_option, "1")
# Write to variables.mak.
write_to_file(os.path.join(self.generated_dir, "variables.mak"),
"\n".join(variables_contents))
# Generate Output Format to output_format.ld.
output_format_contents = export.get_linker_output_format(
self.soc.cpu)
write_to_file(os.path.join(self.generated_dir, "output_format.ld"),
output_format_contents)
# Generate Memory Regions to regions.ld.
regions_contents = export.get_linker_regions(self.soc.mem_regions)
write_to_file(os.path.join(self.generated_dir, "regions.ld"),
regions_contents)
# Generate Memory Regions to mem.h.
mem_contents = export.get_mem_header(self.soc.mem_regions)
write_to_file(os.path.join(self.generated_dir, "mem.h"), mem_contents)
# Generate Memory Regions to memory.x if specified.
if self.memory_x is not None:
memory_x_contents = export.get_memory_x(self.soc)
write_to_file(os.path.realpath(self.memory_x), memory_x_contents)
# Generate SoC Config/Constants to soc.h.
soc_contents = export.get_soc_header(self.soc.constants)
write_to_file(os.path.join(self.generated_dir, "soc.h"), soc_contents)
# Generate CSR registers definitions/access functions to csr.h.
csr_contents = export.get_csr_header(
regions=self.soc.csr_regions,
constants=self.soc.constants,
csr_base=self.soc.mem_regions['csr'].origin)
write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents)
# Generate Git SHA1 of tools to git.h
git_contents = export.get_git_header()
write_to_file(os.path.join(self.generated_dir, "git.h"), git_contents)
# Generate LiteDRAM C header to sdram_phy.h when the SoC use it.
if hasattr(self.soc, "sdram"):
from litedram.init import get_sdram_phy_c_header
sdram_contents = get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing)
write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"),
sdram_contents)
