def __init__(self,
toolchain="trellis",
sys_clk_freq=int(48e6),
sdram_module_cls="AS4C32M8",
**kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Hackaday Badge",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M8(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
def __init__(self,
toolchain="trellis",
sys_clk_freq=int(48e6),
sdram_module_cls="AS4C32M8",
**kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Hackaday Badge",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M8(sys_clk_freq, "1:1"),
l2_cache_size=kwargs.get("l2_size", 8192))
def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
sdram_module = AS4C32M8(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
