def __init__(self, toolchain="trellis", **kwargs):
platform = camlink_4k.Platform(toolchain=toolchain)
sys_clk_freq = int(81e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Cam Link 4K",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Leds -------------------------------------------------------------------------------------
if platform.lookup_request("serial", loose=True) is None: # Disable leds when serial is used.
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="diamond",
integrated_rom_size=0x8000,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
**kwargs)
# crg
crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41J256M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16",
sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] == "usb_acm":
# FIXME: do proper install of ValentyUSB.
os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
else:
platform.add_extension(orangecrab.feather_serial)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on OrangeCrab",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K64M16": MT41K64M16,
"MT41K128M16": MT41K128M16,
"MT41K256M16": MT41K256M16,
"MT41K512M16": MT41K512M16,
}
sdram_module = available_sdram_modules.get(sdram_device)
ddram_pads = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(
pads = ddram_pads,
sys_clk_freq = sys_clk_freq)
self.ddrphy.settings.rtt_nom = "disabled"
self.add_csr("ddrphy")
if hasattr(ddram_pads, "vccio"):
self.comb += ddram_pads.vccio.eq(0b111111)
if hasattr(ddram_pads, "gnd"):
self.comb += ddram_pads.gnd.eq(0)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = sdram_module(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self, toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
sys_clk_freq = int(75e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type="vexriscv",
integrated_rom_size=0x8000,
**kwargs)
# crg
if not self.integrated_main_ram_size:
crg = DDR3TestCRG(platform, sys_clk_freq)
else:
crg = RGMIITestCRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_constant("ECP5DDRPHY", None)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# led blinking
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[26])
def __init__(self, toolchain="trellis", **kwargs):
platform = camlink_4k.Platform(toolchain=toolchain)
sys_clk_freq = int(81e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Cam Link 4K",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
platform = orangecrab.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------_-----------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
def __init__(self,
sys_clk_freq=int(48e6),
toolchain="diamond",
integrated_rom_size=0x8000,
**kwargs):
platform = orangecrab.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore -----------------------------------------------------------------_----------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self,
revision="rev0",
device="45F",
sdram_device="MT41K512M16",
sys_clk_freq=int(75e6),
with_ethernet=False,
toolchain="trellis",
**kwargs):
platform = logicbone.Platform(revision=revision,
device=device,
toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] == "usb_acm":
# FIXME: do proper install of ValentyUSB.
os.system(
"git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri"
)
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Logicbone",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K512M16": MT41K512M16,
#"AS4C1GM8": AS4C1GM8, ## Too many rows, seems to break things.
}
sdram_module = available_sdram_modules.get(sdram_device)
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=sdram_module(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(75e6),
device="LFE5UM5G",
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_phy=0,
toolchain="trellis",
**kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
# FIXME: adapt integrated rom size for Microwatt
if kwargs.get("cpu_type", None) == "microwatt":
kwargs["integrated_rom_size"] = 0xb000 if with_ethernet else 0x9000
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Versa ECP5",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(80e6),
toolchain="trellis",
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = fpc_iii.Platform(toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] == "serial":
# Defaults to USB FIFO since no real serial.
kwargs["uart_name"] = "usb_fifo"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on FPC-III",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
ddram = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(
ddram, sys_clk_freq, clk_polarity=1) # clk_p/n swapped.
self.ddrphy.settings.rtt_nom = "disabled"
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits))
self.add_sdram("sdram",
phy=self.ddrphy,
module=IS43TR16256A(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x20000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
self.comb += platform.request("dram_vtt_en").eq(
0 if self.integrated_main_ram_size else 1)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
device="85F",
sys_clk_freq=int(75e6),
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = ecpix5.Platform(device=device, toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on ECPIX-5",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K256M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
leds_pads = []
for i in range(4):
rgb_led_pads = platform.request("rgb_led", i)
self.comb += [getattr(rgb_led_pads, n).eq(1)
for n in "gb"] # Disable Green/Blue Leds.
leds_pads += [getattr(rgb_led_pads, n) for n in "r"]
self.submodules.leds = LedChaser(pads=Cat(leds_pads),
sys_clk_freq=sys_clk_freq)
def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16",
sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=True, **kwargs):
platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] in ["serial", "usb_acm"]:
kwargs["uart_name"] = "usb_acm"
# Defaults to USB ACM through ValentyUSB.
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on OrangeCrab",
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K64M16": MT41K64M16,
"MT41K128M16": MT41K128M16,
"MT41K256M16": MT41K256M16,
"MT41K512M16": MT41K512M16,
}
sdram_module = available_sdram_modules.get(sdram_device)
ddram_pads = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(
pads = ddram_pads,
sys_clk_freq = sys_clk_freq,
cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
self.ddrphy.settings.rtt_nom = "disabled"
if hasattr(ddram_pads, "vccio"):
self.comb += ddram_pads.vccio.eq(0b111111)
if hasattr(ddram_pads, "gnd"):
self.comb += ddram_pads.gnd.eq(0)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = sdram_module(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
with_led_chaser=True,
with_pmod_gpio=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(trellisboard.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(12)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
self.add_ram("firmware_ram", 0x20000000, 0x10000)
def __init__(self,
sys_clk_freq=int(75e6),
device="LFE5UM5G-45F-8BG381C",
with_ethernet=False,
toolchain="trellis",
**kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
# Fix ROM size for Microwatt
if with_ethernet:
kwargs["integrated_rom_size"] = 0xb000
else:
kwargs["integrated_rom_size"] = 0x9000
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
platform = ecpix5.Platform(toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on ECPIX-5",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K256M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0e-9)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds (Disable...) ------------------------------------------------------------------------
for i in range(4):
rgb_led_pads = platform.request("rgb_led", i)
for c in "rgb":
self.comb += getattr(rgb_led_pads, c).eq(1)
def __init__(self,
revision="0.2",
device="25F",
sdram_device="MT41K64M16",
sys_clk_freq=int(48e6),
toolchain="trellis",
**kwargs):
platform = orangecrab.Platform(revision=revision,
device=device,
toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
platform.add_extension(orangecrab.feather_serial)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
'MT41K64M16': MT41K64M16,
'MT41K128M16': MT41K128M16,
'MT41K256M16': MT41K256M16,
# 'MT41K512M16': MT41K512M16
}
sdram_module = available_sdram_modules.get(sdram_device)
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy=self.ddrphy,
module=sdram_module(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41J256M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self, toolchain="diamond"):
platform = versa_ecp5.Platform(toolchain=toolchain)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type=None,
l2_size=32,
with_uart=None,
csr_data_width=32,
ident="Versa ECP5 test SoC",
ident_version=True)
# crg
crg = DDR3TestCRG(platform, sys_clk_freq)
self.submodules.crg = crg
# uart
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# led blinking
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[26])
# analyzer
analyzer_signals = [
self.ddrphy.dfi.p0, self.ddrphy.datavalid, self.ddrphy.burstdet
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 128)
def __init__(self, toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
# crg
crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_constant("ECP5DDRPHY", None)
ddrphy_init = ECP5DDRPHYInit(self.crg, self.ddrphy)
self.submodules += ddrphy_init
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="diamond",
integrated_rom_size=0x8000,
**kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# https://github.com/enjoy-digital/litex/issues/234
# https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/gpio.py
# /repos/litex/litex-boards/litex_boards/official/platforms/versa_ecp5.py
self.add_csr("gpio_leds")
self.submodules.gpio_leds = GPIOOut(
Cat([platform.request("user_led", i) for i in range(8)]))
# add spi master, from ~/repos/litex/litex/litex/soc/cores
self.add_csr("spi_test")
spi_test = SPIMaster(platform.request("spi_test", 1), 8, sys_clk_freq,
int(sys_clk_freq / 5))
self.submodules.spi_test = spi_test
self.add_csr("dac_test")
dac_test = DAC7563Core(platform.request("dac_test", 1))
self.submodules.dac_test = dac_test
# https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers litescope bridge
# added io to platform, serial_wb
self.submodules.bridge = UARTWishboneBridge(platform.request(
"serial_wb", 1),
sys_clk_freq,
baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
print("creating DDR3 SDRAM")
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
self.add_csr("memory_test")
memory_test = MemtestCore(self.sdram.crossbar.get_port())
self.submodules.memory_test = memory_test
self.add_csr("adc_test")
adc_test = AD7984Core(self.sdram.crossbar.get_port(),
platform.request("adc_test", 1))
self.submodules.adc_test = adc_test
# litescope, track spi
self.add_csr("analyzer")
analyzer_signals = [
dac_test.dac.dac_load,
dac_test._load.fields.load,
dac_test.dac.load,
dac_test.dac.dac_cs,
dac_test.dac.dac_sck,
dac_test.dac.dac_sdi,
dac_test.dac.dac_ready,
dac_test.dac.state,
]
analyzer_depth = 256 # samples
analyzer_clock_domain = "sys"
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
analyzer_depth,
clock_domain=analyzer_clock_domain)
def __init__(self,
sys_clk_freq=int(75e6),
cpu_count=1,
with_ethernet=False,
**kwargs):
VexRiscvSMP.litedram_width = 128
VexRiscvSMP.ibus_width = 64
VexRiscvSMP.dbus_width = 64
VexRiscvSMP.coherent_dma = True
platform = trellisboard.Platform(toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_size"] = 0x10000
kwargs["csr_data_width"] = 8
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_cls=VexRiscvSMP,
cpu_variant="default",
**kwargs)
self.add_constant("config_cpu_count", cpu_count) # for dts generation
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0C00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(pads=PHYPadsReducer(
platform.request("ddram"), [0, 1]),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True,
controller_settings=ControllerSettings(
cmd_buffer_buffered=False,
with_auto_precharge=False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
# Board Revision ---------------------------------------------------------------------------
revision = kwargs.get("revision", "0.2")
device = kwargs.get("device", "25F")
platform = orangecrab.Platform(revision=revision,
device=device,
toolchain=toolchain)
platform.add_extension(extras)
# Disconnect Serial Debug (Stub required so BIOS is kept happy)
kwargs['uart_name'] = "stream"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
csr_data_width=32,
**kwargs)
# connect UART stream to NULL
self.comb += self.uart.source.ready.eq(1)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = crg = CRG(platform,
sys_clk_freq,
with_usb_pll=True)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K64M16": MT41K64M16,
"MT41K128M16": MT41K128M16,
"MT41K256M16": MT41K256M16,
"MT41K512M16": MT41K512M16,
}
sdram_module = available_sdram_modules.get(
kwargs.get("sdram_device", "MT41K64M16"))
ddram_pads = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(pads=ddram_pads,
sys_clk_freq=sys_clk_freq)
self.ddrphy.settings.rtt_nom = "disabled"
self.add_csr("ddrphy")
if hasattr(ddram_pads, "vccio"):
self.comb += ddram_pads.vccio.eq(0b111111)
if hasattr(ddram_pads, "gnd"):
self.comb += ddram_pads.gnd.eq(0)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=sdram_module(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# RGB LED
self.submodules.rgb = RGB(platform.request("rgb_led", 0))
#self.submodules.gpio = GPIOTristateCustom(platform.request("gpio", 0))
self.submodules.gpio = IOPort(platform.request("gpio", 0))
try:
self.submodules.button = GPIOIn(platform.request("usr_btn"))
except:
...
# Analog Mux
#self.submodules.asense = AnalogSense(platform.request("analog"))
# drive PROGRAMN HIGH
self.comb += platform.request("rst_n").eq(1)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads,
dummy=6,
endianness="little")
self.lxspi.add_clk_primitive(platform.device)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.lxspi.bus,
size=16 * 1024 * 1024)
# Attach USB to a seperate CSR bus that's decoupled from our CPU clock
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.submodules.usb0 = CSRClockDomainWrapper(usb_iobuf)
self.comb += self.cpu.interrupt[self.interrupt_map['usb']].eq(
self.usb0.irq)
from litex.soc.integration.soc_core import SoCRegion
self.bus.add_slave(
'usb', self.usb0.bus,
SoCRegion(origin=0x90000000, size=0x1000, cached=False))
self.constants[
"FLASH_BOOT_ADDRESS"] = self.mem_map['spiflash'] + 0x00100000
def __init__(self, platform, with_hdmi_in=False):
sys_clk_freq = int(81e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# HDMI In ----------------------------------------------------------------------------------
if with_hdmi_in:
from litedram.frontend.fifo import LiteDRAMFIFO
hdmi_layout = [("de", 1), ("hsync", 1), ("vsync", 1), ("r", 8),
("g", 8), ("b", 8)]
hdmi_pads = platform.request("hdmi_in")
self.clock_domains.cd_hdmi = ClockDomain()
self.comb += self.cd_hdmi.clk.eq(hdmi_pads.pclk)
# FIXME: Check hdmi_clk freq vs sys_clk freq
cdc = stream.AsyncFIFO(hdmi_layout, 4)
cdc = ClockDomainsRenamer({"write": "hdmi", "read": "sys"})(cdc)
converter = stream.Converter(32, 128)
self.submodules += cdc, converter
fifo_base = 0x00100000 # FIXME: Add control
fifo_depth = 0x00100000 # FIXME: Add control
fifo = LiteDRAMFIFO(
data_width=128,
base=fifo_base,
depth=fifo_depth,
write_port=self.sdram.crossbar.get_port(mode="write"),
write_threshold=fifo_depth - 32,
read_port=self.sdram.crossbar.get_port(mode="read"),
read_threshold=32)
self.submodules += fifo
self.sync.hdmi += [
cdc.sink.valid.eq(1), # FIXME: Add control
cdc.sink.de.eq(hdmi_pads.de),
cdc.sink.hsync.eq(hdmi_pads.hsync),
cdc.sink.vsync.eq(hdmi_pads.vsync),
cdc.sink.r.eq(hdmi_pads.r),
cdc.sink.g.eq(hdmi_pads.g),
cdc.sink.b.eq(hdmi_pads.b),
]
self.comb += cdc.source.connect(converter.sink,
keep={"valid", "ready"})
self.comb += converter.sink.data.eq(cdc.source.payload.raw_bits())
self.comb += converter.source.connect(fifo.sink)
self.comb += fifo.source.ready.eq(
1) # FIXME: to FX3, always ready for now
def __init__(self,
sys_clk_freq=int(50e6),
toolchain="trellis",
with_video_colorbars=False,
with_video_terminal=True,
with_video_framebuffer=False,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
**kwargs):
platform = rcs_arctic_tern_bmc_card.Platform(toolchain=toolchain)
#bios_flash_offset = 0x400000
# Set CPU variant / reset address
#kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
kwargs["integrated_rom_size"] = 0x10000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
platform,
irq_n_irqs=16,
clk_freq=sys_clk_freq,
ident="LiteX SoC on Arctic Tern (BMC card carrier)",
#integrated_main_ram_size = 0x40000,
#integrated_main_ram_size = 0,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(
sys_clk_freq, "1:2"
), # Not MT41J256M16, but the AS4C256M16D3C in use has similar specifications
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", 0),
pads=self.platform.request("eth", 0),
tx_delay=0e-9,
rx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Video Output -----------------------------------------------------------------------------
if with_video_colorbars or with_video_terminal or with_video_framebuffer:
dvo_pads = platform.request("dvo")
self.submodules.videophy = VideoGenericPHY(
dvo_pads, clock_domain="dvo", with_clk_ddr_output=False)
if with_video_terminal:
#self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="dvo")
#self.add_video_terminal(phy=self.videophy, timings="1920x1200@60Hz", clock_domain="dvo")
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="dvo")
elif with_video_framebuffer:
#self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="dvo")
#self.add_video_framebuffer(phy=self.videophy, timings="1920x1200@60Hz", clock_domain="dvo")
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="dvo")
else:
self.add_video_colorbars(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="dvo")
def __init__(self,
revision="1.0",
device="25F",
sys_clk_freq=int(60e6),
toolchain="trellis",
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_spi_flash=False,
with_led_chaser=True,
**kwargs):
platform = butterstick.Platform(revision=revision,
device=device,
toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "crossover"
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on ButterStick",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
with_master=False)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.comb += platform.request("user_led_color").eq(0b010) # Blue.
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis",
with_led_chaser = True,
with_video_terminal = True,
with_video_framebuffer = False,
**kwargs):
platform = ecp5_vip.Platform(toolchain=toolchain)
#bios_flash_offset = 0x400000
# Set CPU variant / reset address
#kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
kwargs["integrated_rom_size"] = 0x10000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ECP5 Evaluation Board",
#integrated_main_ram_size = 0x4000,
#integrated_main_ram_size = 0,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"), # Not entirely MT41J64M16 but similar and works(c)
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
pads = platform.request("hdmi")
self.submodules.videophy = VideoVGAPHY(pads, clock_domain="hdmi")
self.submodules.videoi2c = I2CMaster(pads)
# # 1920x1080@60Hz
# pixel_clock_hz = 160e6
# framerate_hz = 60
# pixels_horizontal = 2200
# pixels_vertical = 1125
# 800x600@60Hz
pixel_clock_hz = 40e6
framerate_hz = 60
pixels_horizontal = 1056
pixels_vertical = 628
# # 1920x1080@30Hz
# pixel_clock_hz = 80e6
# framerate_hz = 30
# pixels_horizontal = 2640
# pixels_vertical = 1125
self.videoi2c.add_init(addr=0x3B, init=[
(0xc7, 0x00), # HDMI configuration
(0xc7, 0x00), # Write twice, the first transfer fails for some reason
(0x1e, 0x00), # Power up transmitter
(0x08, 0x60), # Input Bus/Pixel Repetition (default)
(0x00, int((pixel_clock_hz/1e4) %256)), # Pixel clock in MHz * 100
(0x01, int((pixel_clock_hz/1e4)//256)), #
(0x02, int((framerate_hz*100) %256)), # Framerate * 100
(0x03, int((framerate_hz*100)//256)), #
(0x04, int((pixels_horizontal) %256)), # Pixels horizontal
(0x05, int((pixels_horizontal)//256)), #
(0x06, int((pixels_vertical) %256)), # Pixels vertical
(0x07, int((pixels_vertical)//256)), #
(0x1a, 0x00) # end
])
if with_video_terminal:
#self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
#self.add_video_terminal(phy=self.videophy, timings="1920x1080@30Hz", clock_domain="hdmi")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
if with_video_framebuffer:
#self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self,
device="85F",
sys_clk_freq=int(75e6),
with_ethernet=False,
with_etherbone=False,
with_video_terminal=False,
with_video_framebuffer=False,
with_led_chaser=True,
**kwargs):
platform = ecpix5.Platform(device=device, toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on ECPIX-5",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# HDMI -------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
# PHY + IT6613 I2C initialization.
hdmi_pads = platform.request("hdmi")
self.submodules.videophy = VideoDVIPHY(hdmi_pads,
clock_domain="init")
self.submodules.videoi2c = I2CMaster(hdmi_pads)
# I2C initialization adapted from https://github.com/ultraembedded/ecpix-5
# Copyright (c) 2020 https://github.com/ultraembedded
# Adapted from C to Python.
REG_TX_SW_RST = 0x04
B_ENTEST = (1 << 7)
B_REF_RST = (1 << 5)
B_AREF_RST = (1 << 4)
B_VID_RST = (1 << 3)
B_AUD_RST = (1 << 2)
B_HDMI_RST = (1 << 1)
B_HDCP_RST = (1 << 0)
REG_TX_AFE_DRV_CTRL = 0x61
B_AFE_DRV_PWD = (1 << 5)
B_AFE_DRV_RST = (1 << 4)
B_AFE_DRV_PDRXDET = (1 << 2)
B_AFE_DRV_TERMON = (1 << 1)
B_AFE_DRV_ENCAL = (1 << 0)
REG_TX_AFE_XP_CTRL = 0x62
B_AFE_XP_GAINBIT = (1 << 7)
B_AFE_XP_PWDPLL = (1 << 6)
B_AFE_XP_ENI = (1 << 5)
B_AFE_XP_ER0 = (1 << 4)
B_AFE_XP_RESETB = (1 << 3)
B_AFE_XP_PWDI = (1 << 2)
B_AFE_XP_DEI = (1 << 1)
B_AFE_XP_DER = (1 << 0)
REG_TX_AFE_ISW_CTRL = 0x63
B_AFE_RTERM_SEL = (1 << 7)
B_AFE_IP_BYPASS = (1 << 6)
M_AFE_DRV_ISW = (7 << 3)
O_AFE_DRV_ISW = 3
B_AFE_DRV_ISWK = 7
REG_TX_AFE_IP_CTRL = 0x64
B_AFE_IP_GAINBIT = (1 << 7)
B_AFE_IP_PWDPLL = (1 << 6)
M_AFE_IP_CKSEL = (3 << 4)
O_AFE_IP_CKSEL = 4
B_AFE_IP_ER0 = (1 << 3)
B_AFE_IP_RESETB = (1 << 2)
B_AFE_IP_ENC = (1 << 1)
B_AFE_IP_EC1 = (1 << 0)
REG_TX_HDMI_MODE = 0xC0
B_TX_HDMI_MODE = 1
B_TX_DVI_MODE = 0
REG_TX_GCP = 0xC1
B_CLR_AVMUTE = 0
B_SET_AVMUTE = 1
B_TX_SETAVMUTE = (1 << 0)
B_BLUE_SCR_MUTE = (1 << 1)
B_NODEF_PHASE = (1 << 2)
B_PHASE_RESYNC = (1 << 3)
self.videoi2c.add_init(
addr=0x4c,
init=[
# Reset.
(REG_TX_SW_RST, B_REF_RST | B_VID_RST | B_AUD_RST
| B_AREF_RST | B_HDCP_RST),
(REG_TX_SW_RST, 0),
# Select DVI Mode.
(REG_TX_HDMI_MODE, B_TX_DVI_MODE),
# Configure Clks.
(REG_TX_SW_RST, B_AUD_RST | B_AREF_RST | B_HDCP_RST),
(REG_TX_AFE_DRV_CTRL, B_AFE_DRV_RST),
(REG_TX_AFE_XP_CTRL, 0x18),
(REG_TX_AFE_ISW_CTRL, 0x10),
(REG_TX_AFE_IP_CTRL, 0x0C),
# Enable Clks.
(REG_TX_AFE_DRV_CTRL, 0),
# Enable Video.
(REG_TX_GCP, 0),
])
# Video Terminal/Framebuffer.
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
leds_pads = []
for i in range(4):
rgb_led_pads = platform.request("rgb_led", i)
self.comb += [getattr(rgb_led_pads, n).eq(1)
for n in "gb"] # Disable Green/Blue Leds.
leds_pads += [getattr(rgb_led_pads, n) for n in "r"]
self.submodules.leds = LedChaser(pads=Cat(leds_pads),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
with_video_terminal=False,
with_video_framebuffer=False,
with_led_chaser=True,
with_pmod_gpio=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# HDMI -------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
# PHY + TP410 I2C initialization.
hdmi_pads = platform.request("hdmi")
self.submodules.videophy = VideoDVIPHY(hdmi_pads,
clock_domain="init")
self.submodules.videoi2c = I2CMaster(hdmi_pads)
self.videoi2c.add_init(
addr=0x38,
init=[(0x08, 0x35
) # CTL_1_MODE: Normal operation, 24-bit, HSYNC/VSYNC.
])
# Video Terminal/Framebuffer.
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(trellisboard.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
