def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# mac
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, core_config):
# PHY --------------------------------------------------------------------------------------
PHYCore.__init__(self, platform, core_config)
# MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = core_config["endianness"])
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
# Wishbone Interface -----------------------------------------------------------------------
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
self.wishbone.data_width = 32
bridge = _WishboneBridge(self.platform.request("wishbone"))
self.submodules += bridge
self.add_wb_master(bridge.wishbone)
# Interrupt Interface ----------------------------------------------------------------------
self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)
def __init__(self, **kwargs):
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, toolchain="diamond", **kwargs):
BaseSoC.__init__(self,
toolchain=toolchain,
integrated_rom_size=0x10000,
**kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"), self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
def __init__(self,
phy,
mac_address,
ip_address,
clk_freq,
with_icmp=True,
dw=8):
if isinstance(ip_address, str):
ip_address = convert_ip(ip_address)
self.submodules.mac = LiteEthMAC(phy,
dw,
interface="crossbar",
with_preamble_crc=True)
self.submodules.arp = LiteEthARP(self.mac,
mac_address,
ip_address,
clk_freq,
dw=dw)
self.submodules.ip = LiteEthIP(self.mac,
mac_address,
ip_address,
self.arp.table,
dw=dw)
if with_icmp:
self.submodules.icmp = LiteEthICMP(self.ip, ip_address, dw=dw)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM to fit the BIOS with TFTP support.
dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
BaseSoC.__init__(self, platform, *args, **kwargs)
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYRGMII(
platform.request("eth_clocks"),
platform.request("eth"))
self.add_csr("ethphy")
# Ethernet MAC
ethmac_win_size = 0x2000
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, ethmac_win_size)
self.add_memory_region("ethmac", self.mem_map["ethmac"], ethmac_win_size, type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
#self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, eth_port=0, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYMII(
self.platform.request("eth_clocks", eth_port),
self.platform.request("eth", eth_port))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.platform.add_period_constraint(
self.platform.lookup_request("eth_clocks").tx, 1e9 / 12.5e6)
self.platform.add_period_constraint(
self.platform.lookup_request("eth_clocks").rx, 1e9 / 12.5e6)
self.platform.add_false_path_constraints(
self.platform.lookup_request("clk12"),
self.platform.lookup_request("eth_clocks").tx,
self.platform.lookup_request("eth_clocks").rx)
def __init__(self, phy="rgmii", **kwargs):
assert phy in ["rgmii", "1000basex"]
BaseSoC.__init__(self, **kwargs)
if phy == "rgmii":
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
if phy == "1000basex":
self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
qpll_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
refclk125 = self.platform.request("gtp_refclk")
refclk125_se = Signal()
self.specials += \
Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk125.p,
i_IB=refclk125.n,
o_O=refclk125_se)
qpll = QPLL(refclk125_se, qpll_settings)
self.submodules += qpll
self.submodules.ethphy = A7_1000BASEX(
qpll.channels[0], self.platform.request("sfp", 0),
self.clk_freq)
self.platform.add_period_constraint(self.ethphy.txoutclk,
1e9 / 62.5e6)
self.platform.add_period_constraint(self.ethphy.rxoutclk,
1e9 / 62.5e6)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.txoutclk,
self.ethphy.rxoutclk)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model,
debug=False,
loopback=True)
self.submodules.ethmac = LiteEthMAC(phy=self.phy_model,
dw=32,
interface="wishbone",
with_preamble_crc=True)
def __init__(self, platform, core_config):
# # PHY --------------------------------------------------------------------------------------
# PHYCore.__init__(self, platform, core_config)
# SoC parameters ---------------------------------------------------------------------------
soc_args = {}
if "soc" in core_config:
soc_config = core_config["soc"]
for arg in soc_config:
if arg in ("csr_map", "interrupt_map", "mem_map"):
getattr(self, arg).update(soc_config[arg])
else:
soc_args[arg] = soc_config[arg]
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
clk_freq=core_config["clk_freq"],
**soc_args)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clock"),
platform.request("sys_reset"))
# PHY ----------------------------------------------------------------------------------
ethphy = LiteEthPHYModel(pads=platform.request("model_eth"))
self.submodules.ethphy = ethphy
self.add_csr("ethphy")
# MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=core_config["endianness"])
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
# Wishbone Interface -----------------------------------------------------------------------
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
self.wishbone.data_width = 32
bridge = _WishboneBridge(self.platform.request("wishbone"))
self.submodules += bridge
self.add_wb_master(bridge.wishbone)
# Interrupt Interface ----------------------------------------------------------------------
self.comb += self.platform.request("interrupt_request").eq(
self.ethmac.ev.irq)
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
def __init__(self, phy, clk_freq):
PHYCore.__init__(self, phy, clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
bridge = _WishboneBridge(self.platform.request("wishbone"))
self.submodules += bridge
self.add_wb_master(bridge.wishbone)
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model,
debug=False,
loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model,
mac_address,
ip_address,
debug=False)
self.submodules.mac = LiteEthMAC(self.phy_model,
dw=8,
with_preamble_crc=True)
self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address,
100000)
def add_eth(self, local_ip, remote_ip):
local_ip = local_ip.split(".")
remote_ip = remote_ip.split(".")
self.add_constant("LOCALIP1", int(local_ip[0]))
self.add_constant("LOCALIP2", int(local_ip[1]))
self.add_constant("LOCALIP3", int(local_ip[2]))
self.add_constant("LOCALIP4", int(local_ip[3]))
self.add_constant("REMOTEIP1", int(remote_ip[0]))
self.add_constant("REMOTEIP2", int(remote_ip[1]))
self.add_constant("REMOTEIP3", int(remote_ip[2]))
self.add_constant("REMOTEIP4", int(remote_ip[3]))
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
phy = self.ethphy
# Imports
from liteeth.mac import LiteEthMAC
# MAC
ethmac = LiteEthMAC(phy=phy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.submodules.ethmac = ethmac
name = "ethmac"
ethmac_region = SoCRegion(origin=self.mem_map_zephyr.get(
name, None),
size=0x2000,
cached=False)
self.bus.add_slave(name=name,
slave=ethmac.bus,
region=ethmac_region)
# Timing constraints
if hasattr(phy, "crg"):
eth_rx_clk = phy.crg.cd_eth_rx.clk
eth_tx_clk = phy.crg.cd_eth_tx.clk
else:
eth_rx_clk = phy.cd_eth_rx.clk
eth_tx_clk = phy.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk,
1e9 / phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk,
1e9 / phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
eth_rx_clk, eth_tx_clk)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM to fit the BIOS with TFTP support.
dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
BaseSoC.__init__(self, platform, *args, **kwargs)
# Ethernet ---------------------------------------------------------------------------------
# Ethernet PHY
self.submodules.ethphy = LiteEthPHY(
clock_pads = platform.request("eth_clocks"),
pads = platform.request("eth"),
clk_freq = self.clk_freq)
self.add_csr("ethphy")
# Ethernet MAC
ethmac_win_size = 0x2000
self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, ethmac_win_size)
self.add_memory_region("ethmac", self.mem_map["ethmac"], ethmac_win_size, type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
# FIXME: This is probably too tight?
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
self.platform.add_platform_command("""
# FIXME: ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have
# been found that are not placed at an optimal clock IOB / BUFGMUX site pair.
# The clock IOB component <eth_clocks_rx> is placed at site <K15>.
NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE;
# The IOB component <eth_clocks_tx> is placed at site <K16>.
NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
""",
eth_clocks_rx=platform.lookup_request("eth_clocks").rx,
eth_clocks_tx=platform.lookup_request("eth_clocks").tx,
)
def __init__(self, platform, *args, **kwargs):
# Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0x10000
BaseSoC.__init__(self, platform, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
def __init__(self, phy, clk_freq, endianness):
PHYCore.__init__(self, phy, clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
self.wishbone.data_width = 32
bridge = _WishboneBridge(self.platform.request("wishbone"))
self.submodules += bridge
self.add_wb_master(bridge.wishbone)
self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)
def add_ethernet(self, phy):
# Imports
from liteeth.mac import LiteEthMAC
# MAC
self.submodules.ethmac = LiteEthMAC(
phy = phy,
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
ethmac_region = SoCRegion(size=0x2000, cached=False)
self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# Timing constraints
self.platform.add_period_constraint(phy.crg.cd_eth_rx.clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(phy.crg.cd_eth_tx.clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
phy.crg.cd_eth_rx.clk,
phy.crg.cd_eth_tx.clk)
def __init__(self, platform, core_config):
self.mem_map.update(core_config.get("mem_map", {}))
self.csr_map.update(core_config.get("csr_map", {}))
PHYCore.__init__(self, core_config["phy"], core_config["clk_freq"], platform)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=core_config["endianness"])
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
self.wishbone.data_width = 32
bridge = _WishboneBridge(self.platform.request("wishbone"))
self.submodules += bridge
self.add_wb_master(bridge.wishbone)
self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)
def __init__(self, platform, core_config):
# PHY --------------------------------------------------------------------------------------
PHYCore.__init__(self, platform, core_config)
# MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = core_config["endianness"])
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
# Wishbone Interface -----------------------------------------------------------------------
wb_bus = wishbone.Interface()
self.add_wb_master(wb_bus)
platform.add_extension(wb_bus.get_ios("wishbone"))
self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave")
# Interrupt Interface ----------------------------------------------------------------------
self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.cd_eth_rx.clk,
self.ethphy.cd_eth_tx.clk)
self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
def __init__(self,
with_sdram=False,
with_ethernet=False,
ethernet_phy_model="sim",
with_etherbone=False,
etherbone_mac_address=0x10e2d5000001,
etherbone_ip_address="192.168.1.51",
with_analyzer=False,
sdram_module="MT48LC16M16",
sdram_init=[],
sdram_data_width=32,
sdram_spd_data=None,
sdram_verbosity=0,
with_i2c=False,
with_sdcard=False,
with_spi_flash=False,
spi_flash_init=[],
with_gpio=False,
sim_debug=False,
trace_reset_on=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteX Simulation",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SDRAM ------------------------------------------------------------------------------------
if not self.integrated_main_ram_size and with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
if sdram_spd_data is None:
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(
sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
else:
sdram_module = litedram_modules.SDRAMModule.from_spd_data(
sdram_spd_data, sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module,
data_width=sdram_data_width,
clk_freq=sdram_clk_freq,
verbosity=sdram_verbosity,
init=sdram_init)
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdram_module,
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=False)
if sdram_init != []:
# Skip SDRAM test to avoid corrupting pre-initialized contents.
self.add_constant("SDRAM_TEST_DISABLE")
else:
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024)
# Ethernet / Etherbone PHY -----------------------------------------------------------------
if with_ethernet or with_etherbone:
if ethernet_phy_model == "sim":
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
elif ethernet_phy_model == "xgmii":
self.submodules.ethphy = LiteEthPHYXGMII(None,
self.platform.request(
"xgmii_eth", 0),
model=True)
elif ethernet_phy_model == "gmii":
self.submodules.ethphy = LiteEthPHYGMII(None,
self.platform.request(
"gmii_eth", 0),
model=True)
else:
raise ValueError("Unknown Ethernet PHY model:",
ethernet_phy_model)
# Ethernet and Etherbone -------------------------------------------------------------------
if with_ethernet and with_etherbone:
etherbone_ip_address = convert_ip(etherbone_ip_address)
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=8,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac",
self.mem_map.get("ethmac", None),
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=8)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=8)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=8)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=8)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet:
# Ethernet MAC
self.submodules.ethmac = ethmac = LiteEthMAC(
phy=self.ethphy,
dw=64 if ethernet_phy_model == "xgmii" else 32,
interface="wishbone",
endianness=self.cpu.endianness)
ethmac_region_size = (
ethmac.rx_slots.read() +
ethmac.tx_slots.read()) * ethmac.slot_size.read()
self.add_memory_region("ethmac",
self.mem_map.get("ethmac", None),
ethmac_region_size,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, ethmac.bus,
ethmac_region_size)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
self.add_etherbone(phy=self.ethphy,
ip_address=etherbone_ip_address,
mac_address=etherbone_mac_address)
# I2C --------------------------------------------------------------------------------------
if with_i2c:
pads = platform.request("i2c", 0)
self.submodules.i2c = I2CMasterSim(pads)
# SDCard -----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard("sdcard", use_emulator=True)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.phy.model import LiteSPIPHYModel
from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes
spiflash_module = S25FL128L(Codes.READ_1_1_4)
if spi_flash_init is None:
platform.add_sources(
os.path.abspath(os.path.dirname(__file__)),
"../build/sim/verilog/iddr_verilog.v")
platform.add_sources(
os.path.abspath(os.path.dirname(__file__)),
"../build/sim/verilog/oddr_verilog.v")
self.submodules.spiflash_phy = LiteSPIPHYModel(spiflash_module,
init=spi_flash_init)
self.add_spi_flash(phy=self.spiflash_phy,
mode="4x",
module=spiflash_module,
with_master=True)
# GPIO --------------------------------------------------------------------------------------
if with_gpio:
self.submodules.gpio = GPIOTristate(platform.request("gpio"),
with_irq=True)
self.irq.add("gpio", use_loc_if_exists=True)
# Simulation debugging ----------------------------------------------------------------------
if sim_debug:
platform.add_debug(self, reset=1 if trace_reset_on else 0)
else:
self.comb += platform.trace.eq(1)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# IBus (could also just added as self.cpu.ibus)
self.cpu.ibus.stb,
self.cpu.ibus.cyc,
self.cpu.ibus.adr,
self.cpu.ibus.we,
self.cpu.ibus.ack,
self.cpu.ibus.sel,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r,
# DBus (could also just added as self.cpu.dbus)
self.cpu.dbus.stb,
self.cpu.dbus.cyc,
self.cpu.dbus.adr,
self.cpu.dbus.we,
self.cpu.dbus.ack,
self.cpu.dbus.sel,
self.cpu.dbus.dat_w,
self.cpu.dbus.dat_r,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
def __init__(self,
with_sdram=False,
with_ethernet=False,
with_etherbone=False,
etherbone_mac_address=0x10e2d5000001,
etherbone_ip_address="192.168.1.51",
with_analyzer=False,
sdram_module="MT48LC16M16",
sdram_init=[],
sdram_data_width=32,
sdram_spd_data=None,
sdram_verbosity=0,
with_i2c=False,
with_sdcard=False,
sim_debug=False,
trace_reset_on=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteX Simulation",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SDRAM ------------------------------------------------------------------------------------
if with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
if sdram_spd_data is None:
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(
sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
else:
sdram_module = litedram_modules.SDRAMModule.from_spd_data(
sdram_spd_data, sdram_clk_freq)
phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype,
data_width=sdram_data_width,
clk_freq=sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=sdram_verbosity,
init=sdram_init)
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdram_module,
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=False)
if sdram_init != []:
# Skip SDRAM test to avoid corrupting pre-initialized contents.
self.add_constant("SDRAM_TEST_DISABLE")
else:
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024)
#assert not (with_ethernet and with_etherbone)
if with_ethernet and with_etherbone:
etherbone_ip_address = convert_ip(etherbone_ip_address)
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=8,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=8)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=8)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=8)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=8)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({
"eth_tx": "ethphy_eth_tx",
"eth_rx": "ethphy_eth_rx"
})(ethmac)
self.submodules.ethmac = ethmac
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address=etherbone_mac_address,
ip_address=etherbone_ip_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# IBus (could also just added as self.cpu.ibus)
self.cpu.ibus.stb,
self.cpu.ibus.cyc,
self.cpu.ibus.adr,
self.cpu.ibus.we,
self.cpu.ibus.ack,
self.cpu.ibus.sel,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r,
# DBus (could also just added as self.cpu.dbus)
self.cpu.dbus.stb,
self.cpu.dbus.cyc,
self.cpu.dbus.adr,
self.cpu.dbus.we,
self.cpu.dbus.ack,
self.cpu.dbus.sel,
self.cpu.dbus.dat_w,
self.cpu.dbus.dat_r,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
# I2C --------------------------------------------------------------------------------------
if with_i2c:
pads = platform.request("i2c", 0)
self.submodules.i2c = I2CMasterSim(pads)
self.add_csr("i2c")
# SDCard -----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard("sdcard", use_emulator=True)
# Simulation debugging ----------------------------------------------------------------------
if sim_debug:
platform.add_debug(self, reset=1 if trace_reset_on else 0)
else:
self.comb += platform.trace.eq(1)
def __init__(self,
with_sdram=False,
with_ethernet=False,
with_etherbone=False,
etherbone_mac_address=0x10e2d5000000,
etherbone_ip_address="192.168.1.50",
with_analyzer=False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
ident="LiteX Simulation",
ident_version=True,
with_uart=False,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# Serial -----------------------------------------------------------------------------------
self.submodules.uart_phy = uart.RS232PHYModel(
platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy)
self.add_csr("uart")
self.add_interrupt("uart")
# SDRAM ------------------------------------------------------------------------------------
if with_sdram:
sdram_module = MT48LC16M16(100e6, "1:1") # use 100MHz timings
phy_settings = PhySettings(memtype="SDR",
databits=32,
dfi_databits=16,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024)
assert not (with_ethernet and with_etherbone
) # FIXME: fix simulator with 2 ethernet interfaces
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({
"eth_tx": "ethphy_eth_tx",
"eth_rx": "ethphy_eth_rx"
})(ethmac)
self.submodules.ethmac = ethmac
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# Ethernet ---------------------------------------------------------------------------------
if with_etherbone:
# Ethernet PHY
self.submodules.etherbonephy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("etherbonephy")
# Ethernet MAC
etherbonecore = LiteEthUDPIPCore(self.etherbonephy,
mac_address=etherbone_mac_address,
ip_address=etherbone_ip_address,
clk_freq=sys_clk_freq)
self.submodules.etherbonecore = etherbonecore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.etherbonecore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# FIXME: find interesting signals to probe
self.cpu.ibus,
self.cpu.dbus
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
self.add_csr("analyzer")
def __init__(self,
with_sdram = False,
with_ethernet = False,
with_etherbone = False,
etherbone_mac_address = 0x10e2d5000001,
etherbone_ip_address = "192.168.1.51",
with_analyzer = False,
sdram_module = "MT48LC16M16",
sdram_init = [],
sdram_data_width = 32,
sdram_verbosity = 0,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteX Simulation", ident_version=True,
l2_reverse = False,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SDRAM ------------------------------------------------------------------------------------
if with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
phy_settings = get_sdram_phy_settings(
memtype = sdram_module.memtype,
data_width = sdram_data_width,
clk_freq = sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(
module = sdram_module,
settings = phy_settings,
clk_freq = sdram_clk_freq,
verbosity = sdram_verbosity,
init = sdram_init)
self.register_sdram(
self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
#assert not (with_ethernet and with_etherbone)
if with_ethernet and with_etherbone:
dw = 8
etherbone_ip_address = convert_ip(etherbone_ip_address)
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=dw,
interface = "hybrid",
endianness = self.cpu.endianness,
hw_mac = etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=dw)
self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=dw)
self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=dw)
self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=dw)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
self.add_csr("ethphy")
# Ethernet MAC
ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface = "wishbone",
endianness = self.cpu.endianness)
if with_etherbone:
ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
self.submodules.ethmac = ethmac
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address = etherbone_mac_address,
ip_address = etherbone_ip_address,
clk_freq = sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.cpu.ibus,
self.cpu.dbus
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
self.add_csr("analyzer")
def __init__(self,
sys_clk_freq=int(100e6),
with_etherbone=True,
eth_ip="192.168.1.50",
**kwargs):
platform = sds1104xe.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Siglent SDS1104X-E",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# FIXME: Simplify LiteEth Hybrid MAC integration.
from liteeth.common import convert_ip
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
from liteeth.core.udp import LiteEthUDP
from liteeth.core.icmp import LiteEthICMP
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY
ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.submodules += ethphy
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=ethphy,
dw=8,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# Software Interface.
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Hardware Interface.
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=8)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=8)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=8)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=8)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = ethphy.crg.cd_eth_rx.clk
eth_tx_clk = ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk,
1e9 / ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk,
1e9 / ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
eth_rx_clk, eth_tx_clk)
def __init__(self,
sys_clk_freq=int(100e6),
with_etherbone=True,
eth_ip="192.168.1.50",
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
platform = sds1104xe.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Siglent SDS1104X-E",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_ethernet=with_etherbone)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K64M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# FIXME: Simplify LiteEth Hybrid MAC integration.
from liteeth.common import convert_ip
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
from liteeth.core.udp import LiteEthUDP
from liteeth.core.icmp import LiteEthICMP
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=8,
interface="hybrid",
endianness=self.cpu.endianness,
hw_mac=etherbone_mac_address)
# Software Interface.
self.add_memory_region("ethmac",
getattr(self.mem_map, "ethmac", None),
0x2000,
type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin,
self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Hardware Interface.
self.submodules.arp = LiteEthARP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
sys_clk_freq,
dw=8)
self.submodules.ip = LiteEthIP(self.ethmac,
etherbone_mac_address,
etherbone_ip_address,
self.arp.table,
dw=8)
self.submodules.icmp = LiteEthICMP(self.ip,
etherbone_ip_address,
dw=8)
self.submodules.udp = LiteEthUDP(self.ip,
etherbone_ip_address,
dw=8)
self.add_constant(
"ETH_PHY_NO_RESET"
) # Disable reset from BIOS to avoid disabling Hardware Interface.
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp,
1234,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk
eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk,
1e9 / self.ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk,
1e9 / self.ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
eth_rx_clk, eth_tx_clk)
# Video ------------------------------------------------------------------------------------
video_timings = ("800x480@60Hz", {
"pix_clk": 33.3e6,
"h_active": 800,
"h_blanking": 256,
"h_sync_offset": 210,
"h_sync_width": 1,
"v_active": 480,
"v_blanking": 45,
"v_sync_offset": 22,
"v_sync_width": 1,
})
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("lcd"),
clock_domain="dvi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings=video_timings,
clock_domain="dvi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings=video_timings,
clock_domain="dvi")
def __init__(self,
init_memories=False,
sdram_module="MT48LC16M16",
sdram_data_width=32,
sdram_verbosity=0,
with_ethernet=False):
platform = Platform()
sys_clk_freq = int(1e6)
ram_init = []
if init_memories:
ram_init = get_mem_data(
{
"images/Image": "0x00000000",
"images/rv32.dtb": "0x00ef0000",
"images/rootfs.cpio": "0x01000000",
"images/opensbi.bin": "0x00f00000"
}, "little")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_type="vexriscv_smp",
cpu_variant="linux",
csr_data_width=8,
integrated_rom_size=0x8000,
uart_name="sim")
self.add_constant("SIM")
self.add_constant("config_cpu_count",
VexRiscvSMP.cpu_count) # for dts generation
# Add linker region for OpenSBI
self.add_memory_region("opensbi",
self.mem_map["main_ram"] + 0x00f00000,
0x80000,
type="cached+linker")
self.add_constant("ROM_BOOT_ADDRESS",
self.bus.regions["opensbi"].origin)
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0c00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# Supervisor -------------------------------------------------------------------------------
self.submodules.supervisor = Supervisor()
self.add_csr("supervisor")
# SDRAM ------------------------------------------------------------------------------------
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(
sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype,
data_width=sdram_data_width,
clk_freq=sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=sdram_verbosity,
init=ram_init)
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdram_module,
origin=self.mem_map["main_ram"],
l2_cache_size=0)
self.add_constant(
"SDRAM_TEST_DISABLE"
) # Skip SDRAM test to avoid corrupting pre-initialized contents.
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# eth phy
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0))
self.add_csr("ethphy")
# eth mac
ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=self.cpu.endianness)
self.submodules.ethmac = ethmac
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
def __init__(self,
init_memories = False,
with_sdram = False,
sdram_module = "MT48LC16M16",
sdram_data_width = 32,
sdram_verbosity = 0,
with_ethernet = False):
platform = Platform()
sys_clk_freq = int(1e6)
ram_init = []
if init_memories:
ram_init = get_mem_data({
"buildroot/Image": "0x00000000",
"buildroot/rootfs.cpio": "0x00800000",
"buildroot/rv32.dtb": "0x01000000",
"emulator/emulator.bin": "0x01100000",
}, "little")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
cpu_type = "vexriscv", cpu_variant="linux",
uart_name = "sim",
l2_reverse = False,
max_sdram_size = 0x10000000, # Limit mapped SDRAM to 1GB.
integrated_rom_size = 0x8000,
integrated_main_ram_size = 0x00000000 if with_sdram else 0x02000000, # 32MB
integrated_main_ram_init = [] if (with_sdram or not init_memories) else ram_init)
self.add_constant("SIM", None)
# Supervisor -------------------------------------------------------------------------------
self.submodules.supervisor = Supervisor()
self.add_csr("supervisor")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# Machine mode emulator RAM ----------------------------------------------------------------
self.add_memory_region("emulator", self.mem_map["main_ram"] + 0x01100000, 0x4000, type="cached+linker")
self.add_constant("ROM_BOOT_ADDRESS", self.bus.regions["emulator"].origin)
# SDRAM ------------------------------------------------------------------------------------
if with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
phy_settings = get_sdram_phy_settings(
memtype = sdram_module.memtype,
data_width = sdram_data_width,
clk_freq = sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(
module = sdram_module,
settings = phy_settings,
clk_freq = sdram_clk_freq,
verbosity = sdram_verbosity,
init = ram_init)
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdram_module,
origin = self.mem_map["main_ram"],
size = 0x10000000, # Limit mapped SDRAM to 1GB.
l2_cache_reverse = False)
# FIXME: skip memtest to avoid corrupting memory
self.add_constant("MEMTEST_BUS_SIZE", 0)
self.add_constant("MEMTEST_ADDR_SIZE", 0)
self.add_constant("MEMTEST_DATA_SIZE", 0)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# eth phy
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
self.add_csr("ethphy")
# eth mac
ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.submodules.ethmac = ethmac
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
