def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 25e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 25e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) pwdn = self.platform.request("eth_pwdn", 0) self.comb += pwdn.eq(1) self.submodules.ethphy1 = LiteEthPHYMII( self.platform.request("eth_clocks", 1), self.platform.request("eth", 1), with_hw_init_reset=False) self.add_csr("ethphy1") self.submodules.ethmac1 = LiteEthMAC(phy=self.ethphy1, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_memory_region("ethmac1", self.mem_map["ethmac1"], 0x2000, type="io") self.add_wb_slave(self.mem_map["ethmac1"], self.ethmac1.bus, 0x2000) self.add_csr("ethmac1") self.add_interrupt("ethmac1") self.ethphy1.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy1.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy1.crg.cd_eth_rx.clk, 1e9 / 25e6) self.platform.add_period_constraint(self.ethphy1.crg.cd_eth_tx.clk, 1e9 / 25e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy1.crg.cd_eth_rx.clk, self.ethphy1.crg.cd_eth_tx.clk) pwdn1 = self.platform.request("eth_pwdn", 1) self.comb += pwdn1.eq(1)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = arty.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, interface_type="MEMORY") self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(4)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False): platform = arty.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteDRAM bench on Arty", ident_version=True, integrated_rom_size=0x10000, integrated_rom_mode="rw", uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.A7DDRPHY(pads=PHYPadsReducer( platform.request("ddram"), [0, 1]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], with_bist=with_bist) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), with_hw_init_reset=False) self.add_etherbone(phy=self.ethphy) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [self.ddrphy.dfi] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=256, clock_domain="sys", csr_csv="analyzer.csv") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 12.5e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 25e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 25e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32, l2_size=32) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234)) self.add_wb_master(self.cpu_or_bridge.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(25e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(25e6)) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, sys_clk_freq=int(50e6)): platform = arty.Platform() # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, ident = "LiteEth bench on Arty", ident_version = True ) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), with_hw_init_reset = False) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy, buffer_depth=255) # SRAM ------------------------------------------------------------------------------------- self.add_ram("sram", 0x20000000, 0x1000) # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, **kwargs): platform = c10lprefkit.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # HyperRam --------------------------------------------------------------------------------- self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus) self.add_memory_region("hyperram", self.mem_map["hyperram"], 8 * 1024 * 1024) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy=self.sdrphy, module=MT48LC16M16(sys_clk_freq, "1:1"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs): # Autodetect PHY if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8: if hasattr(clock_pads, "tx"): # This is a 10/100/1G PHY from liteeth.phy.gmii_mii import LiteEthPHYGMIIMII return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs) else: # This is a pure 1G PHY from liteeth.phy.gmii import LiteEthPHYGMII return LiteEthPHYGMII(clock_pads, pads, **kwargs) elif hasattr(pads, "rx_ctl"): # This is a 10/100/1G RGMII PHY raise ValueError( "RGMII PHYs are specific to vendors (for now), use direct instantiation" ) elif len(pads.tx_data) == 4: # This is a MII PHY from liteeth.phy.mii import LiteEthPHYMII return LiteEthPHYMII(clock_pads, pads, **kwargs) else: raise ValueError( "Unable to autodetect PHY from platform file, use direct instantiation" )
def __init__(self, eth_port=0, **kwargs): BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYMII( self.platform.request("eth_clocks", eth_port), self.platform.request("eth", eth_port)) self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) self.add_csr("ethmac") self.add_interrupt("ethmac") self.platform.add_period_constraint( self.platform.lookup_request("eth_clocks").tx, 1e9 / 12.5e6) self.platform.add_period_constraint( self.platform.lookup_request("eth_clocks").rx, 1e9 / 12.5e6) self.platform.add_false_path_constraints( self.platform.lookup_request("clk12"), self.platform.lookup_request("eth_clocks").tx, self.platform.lookup_request("eth_clocks").rx)
def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] + self.shadow_base, 0x2000) platform.add_platform_command( """ NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE; NET "{eth_clocks_rx}" TNM_NET = "GRPeth_rx_clk"; NET "{eth_clocks_tx}" TNM_NET = "GRPeth_tx_clk"; TIMESPEC "TSise_sucks1" = FROM "GRPeth_tx_clk" TO "GRPsys_clk" TIG; TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPeth_tx_clk" TIG; TIMESPEC "TSise_sucks3" = FROM "GRPeth_rx_clk" TO "GRPsys_clk" TIG; TIMESPEC "TSise_sucks4" = FROM "GRPsys_clk" TO "GRPeth_rx_clk" TIG; """, eth_clocks_rx=platform.lookup_request("eth_clocks").rx, eth_clocks_tx=platform.lookup_request("eth_clocks").tx)
def __init__(self, phy, clk_freq): platform = CorePlatform() SoCCore.__init__(self, platform, clk_freq=clk_freq, cpu_type=None, integrated_rom_size=0x0, integrated_sram_size=0x0, integrated_main_ram_size=0x0, csr_address_width=14, csr_data_width=8, with_uart=False, with_timer=False) self.submodules.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset")) # ethernet if phy == "MII": self.submodules.ethphy = LiteEthPHYMII( platform.request("mii_eth_clocks"), platform.request("mii_eth")) elif phy == "RMII": self.submodules.ethphy = LiteEthPHYRMII( platform.request("rmii_eth_clocks"), platform.request("rmii_eth")) elif phy == "GMII": self.submodules.ethphy = LiteEthPHYGMII( platform.request("gmii_eth_clocks"), platform.request("gmii_eth")) elif phy == "RGMII": self.submodules.ethphy = LiteEthPHYRGMII( platform.request("rgmii_eth_clocks"), platform.request("rgmii_eth")) else: ValueError("Unsupported " + phy + " PHY")
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # core self.submodules.ethcore = LiteEthUDPIPCore(phy=self.ethphy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=self.clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 25e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 25e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_uartbone=False, with_jtagbone=False, with_video_terminal=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, **kwargs): self.platform = platform = deca.Platform() # Defaults to JTAG-UART since no hardware UART. real_uart_name = kwargs["uart_name"] if real_uart_name == "serial": if with_jtagbone: kwargs["uart_name"] = "crossover" else: kwargs["uart_name"] = "jtag_uart" if with_uartbone: kwargs["uart_name"] = "crossover" # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Terasic DECA", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False) # UARTbone --------------------------------------------------------------------------------- if with_uartbone: self.add_uartbone(name=real_uart_name, baudrate=kwargs["uart_baudrate"]) # JTAGbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # Ethernet --------------------------------------------------------------------------------- if with_ethernet or with_etherbone: self.platform.toolchain.additional_sdc_commands += [ 'create_clock -name eth_rx_clk -period 40.0 [get_ports {eth_clocks_rx}]', 'create_clock -name eth_tx_clk -period 40.0 [get_ports {eth_clocks_tx}]', 'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_rx_clk}]', 'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_tx_clk}]', 'set_false_path -from [get_clocks {eth_rx_clk}] -to [get_clocks {eth_tx_clk}]', ] self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Video ------------------------------------------------------------------------------------ if with_video_terminal: self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, ident_version=True, with_jtagbone=True, **kwargs): platform = arty.Platform(variant=variant, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", ident_version=ident_version, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, **kwargs): platform = fpc_iii.Platform(toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- if kwargs["uart_name"] == "serial": # Defaults to USB FIFO since no real serial. kwargs["uart_name"] = "usb_fifo" # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on FPC-III", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: ddram = platform.request("ddram") self.submodules.ddrphy = ECP5DDRPHY( ddram, sys_clk_freq, clk_polarity=1) # clk_p/n swapped. self.ddrphy.settings.rtt_nom = "disabled" self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits)) self.add_sdram("sdram", phy=self.ddrphy, module=IS43TR16256A(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x20000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) self.comb += platform.request("dram_vtt_en").eq( 0 if self.integrated_main_ram_size else 1) # Ethernet --------------------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def add_host_bridge(self): self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy, ip_address=self.ip_address, mac_address=self.mac_address, udp_port=self.udp_port)
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, ident_version=True, with_led_chaser=True, with_jtagbone=True, with_spi_flash=False, with_pmod_gpio=False, **kwargs): platform = arty.Platform(variant=variant, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Arty A7", ident_version = ident_version, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K128M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import S25FL128L from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), rate="1:2", with_master=True) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) # GPIOs ------------------------------------------------------------------------------------ if with_pmod_gpio: platform.add_extension(arty.raw_pmod_io("pmoda")) self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = arty.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- if toolchain == "symbiflow": sys_clk_freq = int(60e6) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size and toolchain != "symbiflow": # FIXME self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, interface_type="MEMORY") self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = qmtech_wukong.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on QMTECH Wukong Board", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(105e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, sdram_rate="1:1", **kwargs): platform = qmtech_5cefa2.Platform(with_daughterboard=with_daughterboard) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTECH 5CEFA2" + (" + Daughterboard" if with_daughterboard else ""), **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet = with_ethernet or with_etherbone, with_vga = with_video_terminal or with_video_framebuffer, sdram_rate = sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, ident_version=True, with_jtagbone=True, with_mapped_flash=False, **kwargs): platform = arty.Platform(variant=variant, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Arty A7", ident_version = ident_version, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_mapped_flash) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K128M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # Flash (through LiteSPI, experimental). if with_mapped_flash: self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), S25FL128L(Codes.READ_1_1_4)) self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.cpu.endianness) spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=S25FL128L.total_size, cached=False) self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def add_eth(self, local_ip, remote_ip): local_ip = local_ip.split(".") remote_ip = remote_ip.split(".") self.add_constant("LOCALIP1", int(local_ip[0])) self.add_constant("LOCALIP2", int(local_ip[1])) self.add_constant("LOCALIP3", int(local_ip[2])) self.add_constant("LOCALIP4", int(local_ip[3])) self.add_constant("REMOTEIP1", int(remote_ip[0])) self.add_constant("REMOTEIP2", int(remote_ip[1])) self.add_constant("REMOTEIP3", int(remote_ip[2])) self.add_constant("REMOTEIP4", int(remote_ip[3])) self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) phy = self.ethphy # Imports from liteeth.mac import LiteEthMAC # MAC ethmac = LiteEthMAC(phy=phy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac name = "ethmac" ethmac_region = SoCRegion(origin=self.mem_map_zephyr.get( name, None), size=0x2000, cached=False) self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) # Timing constraints if hasattr(phy, "crg"): eth_rx_clk = phy.crg.cd_eth_rx.clk eth_tx_clk = phy.crg.cd_eth_tx.clk else: eth_rx_clk = phy.cd_eth_rx.clk eth_tx_clk = phy.cd_eth_tx.clk self.platform.add_period_constraint(eth_rx_clk, 1e9 / phy.rx_clk_freq) self.platform.add_period_constraint(eth_tx_clk, 1e9 / phy.tx_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_ethernet=False, with_etherbone=False, **kwargs): platform = c10lprefkit.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on C10 LP RefKit", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # HyperRam --------------------------------------------------------------------------------- self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus) self.add_memory_region("hyperram", self.mem_map["hyperram"], 8 * 1024 * 1024) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy=self.sdrphy, module=MT48LC16M16(sys_clk_freq, "1:1"), l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6)): platform = arty.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_rom_mode="rw", csr_data_width=32, uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"]) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), with_hw_init_reset=False) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, mac_address=0x10e2d5000004, ip_address="10.0.11.2"): BaseSoC.__init__(self, platform, cpu_type="vexriscv", cpu_variant="debug", csr_data_width=8, l2_size=32) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # vexriscv debugging, at offset 0xf00f0000 self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu_or_bridge.debug_bus, 0x10) # Hook Etherbone up to the Wishbone bus, providing Wishbone over Ethernet. etherbone_cd = ClockDomain("etherbone") self.clock_domains += etherbone_cd self.comb += [ etherbone_cd.clk.eq(ClockSignal("sys")), etherbone_cd.rst.eq(ResetSignal("sys")) ] self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master", cd="etherbone") self.add_wb_master(self.etherbone.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(25e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(25e6)) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, sys_clk_freq=int(100e6), with_video_terminal=False, with_video_framebuffer=False, video_timing="1024x600@60Hz", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", **kwargs): platform = qmtech_wukong.Platform() platform.add_extension(qmtech_wukong._sdcard_pmod_io) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTECH Wukong Board", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K128M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings=video_timing, clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(base = 0x4f000000, phy=self.videophy, timings=video_timing, clock_domain="hdmi") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, toolchain="vivado", sys_clk_freq=int(60e6), with_ethernet=False, with_ram=False, board_variant="a7-35", **kwargs): platform = arty.Platform(variant=board_variant, toolchain=toolchain) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", ident_version=False, **kwargs) self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain) # DDR3 SDRAM ------------------------------------------------------------------------------- if with_ram: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) if with_ethernet: self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")