def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs): if with_video_terminal or with_video_framebuffer: sys_clk_freq = int( 148.5e6) # FIXME: For now requires sys_clk >= video_clk. platform = mini_4k.Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["uart_name"] = "jtag_uart" SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Blackmagic Declkink Mini 4K", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoS7GTPHDMIPHY( platform.request("hdmi_out"), sys_clk_freq=sys_clk_freq, clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]" ) # FIXME: Use GTP refclk.
def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=1, cd="sys") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) # pcie msi self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.interrupt) self.interrupts = { "dma_writer": self.dma.writer.irq, "dma_reader": self.dma.reader.irq } for k, v in sorted(self.interrupts.items()): self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v) # flash the led on pcie clock counter = Signal(32) self.sync.clk125 += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs): platform = nereid.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Nereid", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_sdram("sdram", phy = self.ddrphy, module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"), size = 0x40000000, l2_cache_size = kwargs.get("l2_size", 8192) ) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1)
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, with_led_chaser=True, **kwargs): platform = fairwaves_xtrx.Platform() # SoCCore ---------------------------------------------------------------------------------- if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "crossover" SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Fairwaves XTRX", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq, with_pcie) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width = 64, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): platform = vc707.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on VC707", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT8JTF12864(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, platform): sys_clk_freq = int(125e6) SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width=32, ident="LitePCIe example design", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) # PCIe PHY --------------------------------------------------------------------------------- self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1")) self.add_csr("pcie_phy") # PCIe Endpoint ---------------------------------------------------------------------------- self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # PCIe Wishbone bridge --------------------------------------------------------------------- self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1) self.add_wb_master(self.pcie_bridge.wishbone) # PCIe DMA --------------------------------------------------------------------------------- self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.add_csr("pcie_dma") # PCIe MSI --------------------------------------------------------------------------------- self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA_WRITER": self.pcie_dma.writer.irq, "PCIE_DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, variant="a7-35", sys_clk_freq=int(100e6), with_pcie=False, with_ethernet=False, **kwargs): platform = netv2.Platform(variant=variant) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on NeTV2", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=K4B2G1646F(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1, max_pending_requests=2) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, with_led_chaser=True, **kwargs): platform = fairwaves_xtrx.Platform() # SoCCore ---------------------------------------------------------------------------------- if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "crossover" SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Fairwaves XTRX", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq, with_pcie) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width=64, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # ICAP (For FPGA reload over PCIe). from litex.soc.cores.icap import ICAP self.submodules.icap = ICAP() self.icap.add_reload() self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) # Flash (For SPIFlash update over PCIe). FIXME: Should probably be updated to use SpiFlashSingle/SpiFlashDualQuad (so MMAPed and do the update with bit-banging) from litex.soc.cores.gpio import GPIOOut from litex.soc.cores.spi_flash import S7SPIFlash self.submodules.flash_cs_n = GPIOOut( platform.request("flash_cs_n")) self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs): platform = tagus.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tagus", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width=128, bar0_size=0x20000) self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, **kwargs): platform = aller.Platform() # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "crossover" # Defaults to Crossover UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Aller", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, with_uart_bridge=True, **kwargs): clk_freq = 125*1000000 kwargs['cpu_type'] = None SoCCore.__init__(self, platform, clk_freq, shadow_base=0x00000000, csr_data_width=32, with_uart=False, ident="NeTV2 LiteX PCIe SoC", with_timer=False, **kwargs) self.submodules.crg = _CRG(platform) self.submodules.dna = dna.DNA() self.submodules.xadc = xadc.XADC() # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=1) # pci endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.add_cpu_or_bridge(LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)) self.add_wb_master(self.cpu_or_bridge.wishbone) # pcie dma self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) if with_uart_bridge: self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # pcie msi self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.interrupt) self.interrupts = { "dma_writer": self.dma.writer.irq, "dma_reader": self.dma.reader.irq } for k, v in sorted(self.interrupts.items()): self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v) # flash the led on pcie clock counter = Signal(32) self.sync += counter.eq(counter + 1) self.comb += platform.request("user_led", 0).eq(counter[26])
def __init__(self, platform, with_uart_bridge=True): sys_clk_freq = int(125e6) SoCCore.__init__(self, platform, sys_clk_freq, cpu_type=None, shadow_base=0x00000000, csr_data_width=32, with_uart=False, ident="LitePCIe example design", ident_version=True, with_timer=False) self.submodules.crg = _CRG(platform) # PCIe endpoint self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1")) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # PCIe Wishbone bridge self.add_cpu_or_bridge( LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)) self.add_wb_master(self.cpu_or_bridge.wishbone) # PCIe DMA self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) if with_uart_bridge: self.submodules.uart_bridge = UARTWishboneBridge( platform.request("serial"), sys_clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # MSI self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.msi) self.interrupts = { "DMA_WRITER": self.dma.writer.irq, "DMA_READER": self.dma.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): platform = intensity_pro_4k.Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["uart_name"] = "crossover" SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Blackmagic Decklink Intensity Pro 4K", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1)
def __init__(self, platform, with_uart_bridge=True): clk_freq = 125 * 1000000 SoCCore.__init__(self, platform, clk_freq, cpu_type=None, shadow_base=0x00000000, csr_data_width=32, with_uart=False, ident="LitePCIe example design", with_timer=False) self.submodules.crg = _CRG(platform) # PCIe endpoint self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2) self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # PCIe Wishbone bridge self.add_cpu_or_bridge( LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)) self.add_wb_master(self.cpu_or_bridge.wishbone) # PCIe DMA self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) if with_uart_bridge: self.submodules.uart_bridge = UARTWishboneBridge( platform.request("serial"), clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # MSI self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.interrupt) self.interrupts = { "dma_writer": self.dma.writer.irq, "dma_reader": self.dma.reader.irq } for k, v in sorted(self.interrupts.items()): self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v)
def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, csr_data_width=32, **kwargs) # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1")) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.dma.source.connect(self.dma.sink) # pcie msi self.submodules.msi = LitePCIeMSI() self.comb += self.msi.source.connect(self.pcie_phy.msi) self.interrupts = { "DMA_WRITER": self.dma.writer.irq, "DMA_READER": self.dma.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # pcie led pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += self.pcie_led.eq(pcie_counter[26])
def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tagus", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = DNA() self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = XADC() self.add_csr("xadc") # ICAP ------------------------------------------------------------------------------------- self.submodules.icap = ICAP(platform) self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("icap") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # PCIe ------------------------------------------------------------------------------------- # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width=64, bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") # DMA1 self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, with_analyzer=True, with_loopback=False): sys_clk_freq = int(100e6) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, ident="PCIe Screamer", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Serial Wishbone Bridge ------------------------------------------------------------------- self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=3e6) self.add_wb_master(self.bridge.wishbone) # PCIe PHY --------------------------------------------------------------------------------- self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1")) self.add_csr("pcie_phy") # USB FT601 PHY ---------------------------------------------------------------------------- self.submodules.usb_phy = FT601Sync(platform.request("usb_fifo"), dw=32, timeout=1024) # USB Loopback ----------------------------------------------------------------------------- if with_loopback: self.submodules.usb_loopback_fifo = stream.SyncFIFO( phy_description(32), 2048) self.comb += [ self.usb_phy.source.connect(self.usb_loopback_fifo.sink), self.usb_loopback_fifo.source.connect(self.usb_phy.sink) ] # USB Core --------------------------------------------------------------------------------- else: self.submodules.usb_core = USBCore(self.usb_phy, sys_clk_freq) # USB <--> Wishbone -------------------------------------------------------------------- self.submodules.etherbone = Etherbone(self.usb_core, self.usb_map["wishbone"]) self.add_wb_master(self.etherbone.master.bus) # USB <--> TLP ------------------------------------------------------------------------- self.submodules.tlp = TLP(self.usb_core, self.usb_map["tlp"]) self.comb += [ self.pcie_phy.source.connect(self.tlp.sender.sink), self.tlp.receiver.source.connect(self.pcie_phy.sink) ] # Wishbone --> MSI ------------------------------------------------------------------------- self.submodules.msi = MSI() self.comb += self.msi.source.connect(self.pcie_phy.msi) self.add_csr("msi") # Led blink -------------------------------------------------------------------------------- usb_counter = Signal(32) self.sync.usb += usb_counter.eq(usb_counter + 1) self.comb += platform.request("user_led", 0).eq(usb_counter[26]) pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += platform.request("user_led", 1).eq(pcie_counter[26]) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ self.pcie_phy.sink, self.pcie_phy.source, ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, 1024, csr_csv="test/analyzer.csv") self.add_csr("analyzer")
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_pcie=False, with_sata=False, **kwargs): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on KC705", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), clk_freq=self.clk_freq) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter ( "sfp2sata", 0, Subsignal("tx_p", Pins("H2")), Subsignal("tx_n", Pins("H1")), Subsignal("rx_p", Pins("G4")), Subsignal("rx_n", Pins("G3")), ), ] platform.add_extension(_sata_io) # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, refclk=sata_refclk, pads=platform.request("sfp2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCCore --------------------_------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Nereid", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.msis = { "DMA_WRITER": self.pcie_dma.writer.irq, "DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.msis.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, csr_data_width=32, integrated_rom_size=0x10000, integrated_sram_size=0x10000, integrated_main_ram_size= 0x10000, # FIXME: keep this for initial PCIe tests ident="Tagus LiteX Test SoC", ident_version=True, with_uart=not with_pcie_uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = dna.DNA() self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = xadc.XADC() self.add_csr("xadc") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") platform.add_platform_command( "create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_wishbone = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_wishbone.wishbone) # pcie dma self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.msis = { "DMA_WRITER": self.pcie_dma.writer.irq, "DMA_READER": self.pcie_dma.reader.irq } for i, (k, v) in enumerate(sorted(self.msis.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # pcie_uart if with_pcie_uart: class PCIeUART(Module, AutoCSR): def __init__(self, uart): self.rx_valid = CSRStatus() self.rx_ready = CSR() self.rx_data = CSRStatus(8) self.tx_valid = CSR() self.tx_ready = CSRStatus() self.tx_data = CSRStorage(8) # # # # cpu to pcie self.comb += [ self.rx_valid.status.eq(uart.sink.valid), uart.sink.ready.eq(self.rx_ready.re), self.rx_data.status.eq(uart.sink.data), ] # pcie to cpu self.sync += [ If(self.tx_valid.re, uart.source.valid.eq(1)).Elif( uart.source.ready, uart.source.valid.eq(0)) ] self.comb += [ self.tx_ready.status.eq(~uart.source.valid), uart.source.data.eq(self.tx_data.storage) ] uart_interface = RS232PHYInterface() self.submodules.uart = UART(uart_interface) self.add_csr("uart") self.add_interrupt("uart") self.submodules.pcie_uart = PCIeUART(uart_interface) self.add_csr("pcie_uart") # Leds ------------------------------------------------------------------------------------- # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) self.comb += [ platform.request("user_led", 0).eq(1), platform.request("user_led", 1).eq(sys_counter[26]), platform.request("user_led", 2).eq(1), ]
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs): if with_video_terminal or with_video_framebuffer: sys_clk_freq = int( 148.5e6) # FIXME: For now requires sys_clk >= video_clk. platform = mini_4k.Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["uart_name"] = "jtag_uart" SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Blackmagic Decklink Mini 4K", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod). ( "pcie2sata", 0, Subsignal("tx_p", Pins("B7")), Subsignal("tx_n", Pins("A7")), Subsignal("rx_p", Pins("B11")), Subsignal("rx_n", Pins("A11")), ), ] platform.add_extension(_sata_io) # RefClk, Generate 150MHz from PLL. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, refclk=ClockSignal("sata_refclk"), pads=platform.request("pcie2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoS7GTPHDMIPHY( platform.request("hdmi_out"), sys_clk_freq=sys_clk_freq, clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]" ) # FIXME: Use GTP refclk.
def __init__(self, with_pcie=False, **kwargs): platform = acorn_cle_215.Platform() sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Acorn CLE 215+", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K512M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") self.comb += platform.request("pcie_clkreq_n").eq(0) # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, base_address = self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) self.add_csr("pcie_dma0") # DMA1 self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering = True, buffering_depth=1024, with_loopback = True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, speed="gen2", nlanes=4): data_width, sys_clk_freq = self.configs[speed + ":x{}".format(nlanes)] # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__( self, platform, sys_clk_freq, csr_data_width=32, ident="LitePCIe example design on KC705 ({}:x{})".format( speed, nlanes), ident_version=True, with_uart=True, uart_name="bridge") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("crg") # PCIe ------------------------------------------------------------------------------------- # PHY self.submodules.pcie_phy = S7PCIEPHY( platform, platform.request("pcie_x" + str(nlanes)), data_width=data_width, bar0_size=0x20000, ) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, endianness="big", max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") # DMA1 self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i)
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, **kwargs): platform = acorn_cle_215.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Acorn CLE 215+", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K512M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod). ( "pcie2sata", 0, Subsignal("tx_p", Pins("B6")), Subsignal("tx_n", Pins("A6")), Subsignal("rx_p", Pins("B10")), Subsignal("rx_n", Pins("A10")), ), ] platform.add_extension(_sata_io) # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, refclk=sata_refclk, pads=platform.request("pcie2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, eth_phy="rgmii", with_pcie=False, **kwargs): platform = ac701.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on AC701", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # RGMII Ethernet PHY ------------------------------------------------------------------- if eth_phy == "rgmii": # phy self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) # 1000BaseX Ethernet PHY --------------------------------------------------------------- if eth_phy == "1000basex": # phy self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0) self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0) qpll_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) refclk125 = self.platform.request("gtp_refclk") refclk125_se = Signal() self.specials += \ Instance("IBUFDS_GTE2", i_CEB = 0, i_I = refclk125.p, i_IB = refclk125.n, o_O = refclk125_se) qpll = QPLL(refclk125_se, qpll_settings) self.submodules += qpll self.submodules.ethphy = A7_1000BASEX( qpll_channel=qpll.channels[0], data_pads=self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq) self.add_ethernet(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, with_sdram=True, with_ethernet=False, with_etherbone=True, with_sdcard=True, with_pcie=False, with_hdmi_in0=False, with_hdmi_out0=False, with_hdmi_in1=False, with_hdmi_out1=False, with_interboard_communication=False): assert not (with_pcie and with_interboard_communication) sys_clk_freq = int(100e6) sd_freq = int(100e6) SoCSDRAM.__init__(self, platform, sys_clk_freq, #cpu_type="vexriscv", l2_size=32, cpu_type=None, l2_size=32, #csr_data_width=8, csr_address_width=14, csr_data_width=32, csr_address_width=14, integrated_rom_size=0x8000, integrated_sram_size=0x4000, integrated_main_ram_size=0x8000 if not with_sdram else 0, ident="NeTV2 LiteX Test SoC", ident_version=True, reserve_nmi_interrupt=False) # crg self.submodules.crg = CRG(platform, sys_clk_freq) # dnax self.submodules.dna = dna.DNA() # xadc self.submodules.xadc = xadc.XADC() # icap self.submodules.icap = ICAP(platform) # flash self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6)) # sdram if with_sdram: self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # ethernet if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # etherbone if with_etherbone: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq) self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")) self.add_wb_master(self.cpu.wishbone.bus) #self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") #self.add_wb_master(self.etherbone.wishbone.bus) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # sdcard self.submodules.sdclk = SDClockerS7() self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq) self.crg.cd_sys.clk.attr.add("keep") self.sdclk.cd_sd.clk.attr.add("keep") self.sdclk.cd_sd_fb.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.sdclk.cd_sd.clk, self.sdclk.cd_sd_fb.clk) # pcie if with_pcie: # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2")) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000) self.add_wb_master(self.pcie_bridge.wishbone) # pcie dma self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # interboard communication if with_interboard_communication: self.clock_domains.cd_refclk = ClockDomain() self.submodules.refclk_pll = refclk_pll = S7PLL() refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6) refclk_pll.create_clkout(self.cd_refclk, 125e6) platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # qpll qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9) print(qpll) self.submodules += qpll # gtp gtp = GTP(qpll, platform.request("interboard_comm_tx"), platform.request("interboard_comm_rx"), sys_clk_freq, clock_aligner=True, internal_loopback=False) self.submodules += gtp counter = Signal(32) self.sync.tx += counter.eq(counter + 1) # send counter to other-board self.comb += [ gtp.encoder.k[0].eq(1), gtp.encoder.d[0].eq((5 << 5) | 28), gtp.encoder.k[1].eq(0), gtp.encoder.d[1].eq(counter[26:]) ] # receive counter and display it on leds self.comb += [ platform.request("user_led", 3).eq(gtp.rx_ready), platform.request("user_led", 4).eq(gtp.decoders[1].d[0]), platform.request("user_led", 5).eq(gtp.decoders[1].d[1]) ] gtp.cd_tx.clk.attr.add("keep") gtp.cd_rx.clk.attr.add("keep") platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk) # hdmi in 0 if with_hdmi_in0: hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk), for clk in [self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6)) # hdmi out 0 if with_hdmi_out0: hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut( platform.device, platform.request("hdmi_out", 0), hdmi_out0_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # hdmi in 1 if with_hdmi_in1: hdmi_in1_pads = platform.request("hdmi_in", 1) self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in1 = HDMIIn( hdmi_in1_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk), for clk in [self.hdmi_in1.clocking.cd_pix.clk, self.hdmi_in1.clocking.cd_pix1p25x.clk, self.hdmi_in1.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6)) # hdmi out 1 if with_hdmi_out1: hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True) self.submodules.hdmi_out1 = VideoOut( platform.device, platform.request("hdmi_out", 1), hdmi_out1_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk, self.hdmi_out1.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) self.comb += platform.request("user_led", 0).eq(sys_counter[26]) # led blinking (pcie) if with_pcie: pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += platform.request("user_led", 1).eq(pcie_counter[26]) # led blinking (sdcard) if with_sdcard: sd_counter = Signal(32) self.sync.sd += sd_counter.eq(sd_counter + 1) self.comb += platform.request("user_led", 1).eq(sd_counter[26])
def __init__(self, platform, with_cpu=True, with_sdram=True, with_etherbone=True, with_pcie=True, with_sdram_dmas=False, with_hdmi_in0=True, with_hdmi_out0=True): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, sys_clk_freq, cpu_type="vexriscv" if with_cpu else None, cpu_variant="lite", l2_size=128, csr_data_width=32, with_uart=with_cpu, uart_name="crossover", integrated_rom_size=0x8000 if with_cpu else 0x0000, integrated_main_ram_size=0x1000 if not with_sdram else 0x0000, ident="NeTV2 LiteX SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("crg") # DNA -------------------------------------------------------------------------------------- self.submodules.dna = DNA() self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("dna") # XADC ------------------------------------------------------------------------------------- self.submodules.xadc = XADC() self.add_csr("xadc") # ICAP ------------------------------------------------------------------------------------- self.submodules.icap = ICAP(platform) self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) self.add_csr("icap") # Flash ------------------------------------------------------------------------------------ self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6) self.add_csr("flash") # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") sdram_module = K4B2G1646F(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings=sdram_module.geom_settings, timing_settings=sdram_module.timing_settings) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: # ethphy self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # ethcore self.submodules.ethcore = LiteEthUDPIPCore( phy=self.ethphy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=self.clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone( self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 50e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 50e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY ---------------------------------------------------------------------------------- self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width=64, bar0_size=0x20000) platform.add_false_path_constraint(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint ----------------------------------------------------------------------------- self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # Wishbone bridge ---------------------------------------------------------------------- self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 --------------------------------------------------------------------------------- self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") # DMA1 --------------------------------------------------------------------------------- self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma1") self.add_constant("DMA_CHANNELS", 2) # MSI ---------------------------------------------------------------------------------- self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # FIXME : Dummy counter capture, connect to HDMI In ------------------------------------ pcie_dma0_counter = Signal(32) self.sync += [ self.pcie_dma0.sink.valid.eq(1), If(self.pcie_dma0.sink.ready, pcie_dma0_counter.eq(pcie_dma0_counter + 1)), self.pcie_dma0.sink.data.eq(pcie_dma0_counter) ] pcie_dma1_counter = Signal(32) self.sync += [ self.pcie_dma1.sink.valid.eq(1), If(self.pcie_dma1.sink.ready, pcie_dma1_counter.eq(pcie_dma1_counter + 2)), self.pcie_dma1.sink.data.eq(pcie_dma1_counter) ] # SDRAM DMAs ------------------------------------------------------------------------------- if with_sdram_dmas: self.submodules.sdram_reader = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.sdram_reader.add_csr() self.add_csr("sdram_reader") self.submodules.sdram_writer = LiteDRAMDMAReader( self.sdram.crossbar.get_port()) self.sdram_writer.add_csr() self.add_csr("sdram_writer") # HDMI In 0 -------------------------------------------------------------------------------- if with_hdmi_in0: hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.add_csr("hdmi_in0_freq") self.submodules.hdmi_in0 = HDMIIn( pads=hdmi_in0_pads, dram_port=self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.add_csr("hdmi_in0") self.add_csr("hdmi_in0_edid_mem") self.comb += self.hdmi_in0_freq.clk.eq( self.hdmi_in0.clocking.cd_pix.clk), platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk) self.platform.add_period_constraint( platform.lookup_request("hdmi_in", 0).clk_p, 1e9 / 74.25e6) # HDMI Out 0 ------------------------------------------------------------------------------- if with_hdmi_out0: self.submodules.hdmi_out0 = VideoOut( device=platform.device, pads=platform.request("hdmi_out", 0), dram_port=self.sdram.crossbar.get_port( mode="read", data_width=16, clock_domain="hdmi_out0_pix", reverse=True), mode="ycbcr422", fifo_depth=512) self.add_csr("hdmi_out0") platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk)
def __init__(self, variant="cle-215+", sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): platform = acorn.Platform(variant=variant) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Acorn CLE-101/215(+)", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K512M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # FIXME: Apply it to all targets (integrate it in LitePCIe?). platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq) platform.toolchain.pre_placement_commands.add( "set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks userclk2] -asynchronous", sys_clk=self.crg.cd_sys.clk) platform.toolchain.pre_placement_commands.add( "set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks clk_125mhz] -asynchronous", sys_clk=self.crg.cd_sys.clk) platform.toolchain.pre_placement_commands.add( "set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks clk_250mhz] -asynchronous", sys_clk=self.crg.cd_sys.clk) platform.toolchain.pre_placement_commands.add( "set_clock_groups -group [get_clocks clk_125mhz] -group [get_clocks clk_250mhz] -asynchronous" ) # ICAP (For FPGA reload over PCIe). from litex.soc.cores.icap import ICAP self.submodules.icap = ICAP() self.icap.add_reload() self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) # Flash (For SPIFlash update over PCIe). from litex.soc.cores.gpio import GPIOOut from litex.soc.cores.spi_flash import S7SPIFlash self.submodules.flash_cs_n = GPIOOut( platform.request("flash_cs_n")) self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod). ( "pcie2sata", 0, Subsignal("tx_p", Pins("B6")), Subsignal("tx_n", Pins("A6")), Subsignal("rx_p", Pins("B10")), Subsignal("rx_n", Pins("A10")), ), ] platform.add_extension(_sata_io) # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, refclk=sata_refclk, pads=platform.request("pcie2sata"), gen="gen1", clk_freq=sys_clk_freq, data_width=16) # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, platform, with_cpu=False, with_analyzer=True, with_loopback=False): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, cpu_type="lm32" if with_cpu else None, integrated_rom_size=0x8000 if with_cpu else 0, integrated_sram_size=0x8000, with_uart=with_cpu, ident="PCIe Injector example design", with_timer=with_cpu) self.submodules.crg = _CRG(platform) if not with_cpu: # use serial as wishbone bridge when no cpu self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=3000000)) self.add_wb_master(self.cpu_or_bridge.wishbone) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) # pcie endpoint self.submodules.pciephy = S7PCIEPHY(platform, platform.request("pcie_x1"), cd="sys") # usb core usb_pads = platform.request("usb_fifo") # self.submodules.usb_phy = FT245PHYSynchronous(usb_pads, clk_freq, fifo_depth=16) self.submodules.usb_phy = FT601Sync(usb_pads, dw=32, timeout=1024) if with_loopback: self.submodules.usb_loopback_fifo = stream.SyncFIFO( phy_description(32), 2048) self.comb += [ self.usb_phy.source.connect(self.usb_loopback_fifo.sink), self.usb_loopback_fifo.source.connect(self.usb_phy.sink) ] else: self.submodules.usb_core = USBCore(self.usb_phy, clk_freq) # usb <--> wishbone self.submodules.etherbone = Etherbone(self.usb_core, self.usb_map["wishbone"]) self.add_wb_master(self.etherbone.master.bus) # usb <--> tlp self.submodules.tlp = TLP(self.usb_core, self.usb_map["tlp"]) self.comb += [ self.pciephy.source.connect(self.tlp.sender.sink), self.tlp.receiver.source.connect(self.pciephy.sink) ] # wishbone --> msi self.submodules.msi = MSI() self.comb += self.msi.source.connect(self.pciephy.msi) # led blink usb_counter = Signal(32) self.sync.usb += usb_counter.eq(usb_counter + 1) self.comb += platform.request("user_led", 0).eq(usb_counter[26]) pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += platform.request("user_led", 1).eq(pcie_counter[26]) # timing constraints self.crg.cd_sys.clk.attr.add("keep") self.crg.cd_usb.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.crg.cd_usb.clk, 10.0) self.platform.add_period_constraint( self.platform.lookup_request("pcie_x1").clk_p, 10.0) if with_analyzer: analyzer_signals = [ self.pciephy.sink.valid, self.pciephy.sink.ready, self.pciephy.sink.last, self.pciephy.sink.dat, self.pciephy.sink.be, self.pciephy.source.valid, self.pciephy.source.ready, self.pciephy.source.last, self.pciephy.source.dat, self.pciephy.source.be ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024, cd="sys")
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): platform = stlv7325.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on STLV7325", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, ) self.add_sdram( "sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192), ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks", 0), pads=self.platform.request("eth", 0), clk_freq=self.clk_freq) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # TODO verify / test # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") # PHY self.submodules.sata_phy = LiteSATAPHY(platform.device, refclk=sata_refclk, pads=platform.request( "sata", 0), gen="gen2", clk_freq=sys_clk_freq, data_width=16) # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led_n"), sys_clk_freq=sys_clk_freq) # I2C -------------------------------------------------------------------------------------- self.submodules.i2c = I2CMaster(platform.request("i2c"))