def __init__(self, platform): self.submodules.crg = _CRG(platform, int(50e6)) # SRAM self.submodules.sram = wishbone.SRAM(1024) # SD Emulator sdcard_pads = _sdemulator_pads() self.submodules.sdemulator = ClockDomainsRenamer("sd")( SDEmulator(platform, sdcard_pads)) # SD Core self.submodules.sdphy = SDPHY(sdcard_pads, platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.bist_generator = BISTBlockGenerator(random=False) self.submodules.bist_checker = BISTBlockChecker(random=False) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] # Wishbone self.bus = wishbone.Interface() wb_masters = [ self.bus ] wb_slaves = [ (mem_decoder(sram_base), self.sram.bus), (mem_decoder(sdemulator_base), self.sdemulator.bus) ] self.submodules.wb_decoder = wishbone.InterconnectShared(wb_masters, wb_slaves, register=True) # Tester self.submodules.sdtester = SDTester(self.sdcore, self.sdemulator, self.bist_generator, self.bist_checker, self.bus)
def __init__(self, with_cpu, with_emulator, with_analyzer): platform = minispartan6.Platform(device="xc6slx25") platform.add_extension(_sd_io) clk_freq = int(50e6) sd_freq = int(140e6) SoCCore.__init__(self, platform, clk_freq=clk_freq, cpu_type="lm32" if with_cpu else None, csr_data_width=32, with_uart=with_cpu, with_timer=with_cpu, ident="SDCard Test SoC", ident_version=True, integrated_rom_size=0x8000 if with_cpu else 0, integrated_main_ram_size=0x8000 if with_cpu else 0) self.submodules.crg = _CRG(platform, clk_freq) # bridge if not with_cpu: self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) # emulator if with_emulator: sdcard_pads = _sdemulator_pads() self.submodules.sdemulator = SDEmulator(platform, sdcard_pads) else: sdcard_pads = platform.request('sdcard') # sd self.submodules.sdclk = SDClockerS6() self.submodules.sdphy = SDPHY(sdcard_pads, platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9 / sd_freq) self.crg.cd_sys.clk.attr.add("keep") self.sdclk.cd_sd.clk.attr.add("keep") self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.sdclk.cd_sd.clk) # led led_counter = Signal(32) self.sync.sd += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[26]) # analyzer if with_analyzer: analyzer_signals = [ self.sdphy.sdpads, self.sdphy.cmdw.sink, self.sdphy.cmdr.sink, self.sdphy.cmdr.source, self.sdphy.dataw.sink, self.sdphy.datar.sink, self.sdphy.datar.source ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 2048, cd="sd", cd_ratio=4)
def __init__(self, with_cpu, with_emulator, with_analyzer): platform = nexys4ddr.Platform() sys_clk_freq = int(100e6) sd_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv" if with_cpu else None, csr_data_width=32, with_uart=with_cpu, with_timer=with_cpu, ident="SDCard Test SoC", ident_version=True, integrated_rom_size=0x8000 if with_cpu else 0, integrated_main_ram_size=0x8000 if with_cpu else 0) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Serial bridge (optional) ----------------------------------------------------------------- if not with_cpu: self.submodules.bridge = UARTWishboneBridge( platform.request("serial"), sys_clk_freq) self.add_wb_master(self.bridge.wishbone) # SDCard Emulator (optional) --------------------------------------------------------------- if with_emulator: from litesdcard.emulator import SDEmulator, _sdemulator_pads sdcard_pads = _sdemulator_pads() self.submodules.sdemulator = SDEmulator(platform, sdcard_pads) self.add_csr("sdemulator") else: sdcard_pads = platform.request('sdcard') # SDCard ----------------------------------------------------------------------------------- self.comb += sdcard_pads.rst.eq(0) self.submodules.sdclk = SDClockerS7() self.submodules.sdphy = SDPHY(sdcard_pads, platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.add_csr("sdclk") self.add_csr("sdphy") self.add_csr("sdcore") self.add_csr("sdtimer") self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.add_csr("bist_generator") self.add_csr("bist_checker") self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9 / sd_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9 / sd_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.sdclk.cd_sd.clk, self.sdclk.cd_sd_fb.clk) # Led -------------------------------------------------------------------------------------- led_counter = Signal(32) self.sync.sd += led_counter.eq(led_counter + 1) self.comb += platform.request("user_led", 0).eq(led_counter[26]) # Analyzer (optional) ---------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [ self.sdphy.sdpads, self.sdphy.cmdw.sink, self.sdphy.cmdr.sink, self.sdphy.cmdr.source, self.sdphy.dataw.sink, self.sdphy.datar.sink, self.sdphy.datar.source ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, 2048, clock_domain="sd", csr_csv="../test/analyzer.csv") self.add_csr("analyzer")