def main(): parser = argparse.ArgumentParser( description="LiteSATA bench on Nexys Video") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") parser.add_argument("--gen", default="2", help="SATA Gen: 1 or 2 (default)") parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer") args = parser.parse_args() platform = nexys_video.Platform() platform.add_extension(_sata_io) soc = SATATestSoC(platform, "gen" + args.gen, with_analyzer=args.with_analyzer) builder = Builder(soc, csr_csv="csr.csv") builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main(): parser = argparse.ArgumentParser( description="LiteICLink SerWB bench on Nexys Video") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") parser.add_argument("--low-speed", action="store_true", help="Use Low-Speed PHY") parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer") args = parser.parse_args() platform = nexys.Platform() platform.add_extension(serwb_io) soc = SerWBTestSoC(platform, low_speed=args.low_speed, with_analyzer=args.with_analyzer) builder = Builder(soc, csr_csv="csr.csv") builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def main(): parser = argparse.ArgumentParser(description="Nexys LiteX SoC") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() platform = nexys_video.Platform() soc = BaseSoC(platform, **soc_sdram_argdict(args)) builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv") vns = builder.build()
def __init__(self, **kwargs): platform = nexys_video.Platform() SoCCore.__init__(self, platform, clk_freq=100 * 1000000, integrated_rom_size=0x8000, integrated_sram_size=0x8000, integrated_main_ram_size=0x10000, **kwargs) self.submodules.crg = _CRG(platform)
def __init__(self, **kwargs): platform = nexys_video.Platform() SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
def main(): platform = nexys.Platform() platform.add_extension(serwb_io) if len(sys.argv) < 2: print("missing target (base or serwb)") exit() if sys.argv[1] == "base": soc = BaseSoC(platform) elif sys.argv[1] == "serwb": soc = SERDESTestSoC(platform) else: raise KeyError builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv") vns = builder.build() soc.do_exit(vns)
def main(): parser = argparse.ArgumentParser(description="Nexys LiteX SoC") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") parser.add_argument("--nocompile-gateware", action="store_true") args = parser.parse_args() platform = nexys.Platform() cls = MiniSoC if args.with_ethernet else BaseSoC soc = cls(platform, **soc_sdram_argdict(args)) builder = Builder(soc, output_dir="build", compile_gateware=not args.nocompile_gateware, csr_csv="test/csr.csv") vns = builder.build()
def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys_video.Platform() # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT41K256M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings = sdram_module.geom_settings, timing_settings = sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_sata=False, **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Nexys Video", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html ("fmc2sata", 0, Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")), Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")), Subsignal("tx_p", Pins("LPC:DP0_C2M_P")), Subsignal("tx_n", Pins("LPC:DP0_C2M_N")), Subsignal("rx_p", Pins("LPC:DP0_M2C_P")), Subsignal("rx_n", Pins("LPC:DP0_M2C_N"))), ] platform.add_extension(_sata_io) # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, pads=platform.request("fmc2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")