def load(): import os f = open("netv2.cfg", "w") f.write( """ interface bcm2835gpio transport select jtag bcm2835gpio_peripheral_base 0x3F000000 bcm2835gpio_speed_coeffs 100000 5 bcm2835gpio_jtag_nums 4 17 27 22 bcm2835gpio_srst_num 24 reset_config none source [find cpld/xilinx-xc7.cfg] adapter_khz 10000 proc fpga_program {} { global _CHIPNAME xc7_program $_CHIPNAME.tap } """) f.close() from litex.build.openocd import OpenOCD prog = OpenOCD("netv2.cfg") prog.load_bitstream("build/gateware/top.bit")
def main(): with open("README.md") as f: description = [str(f.readline()) for i in range(1, 9)] parser = argparse.ArgumentParser( description="".join(description[1:]), formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") args = parser.parse_args() if args.load: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg") prog.load_bitstream("build/gateware/top.bit") exit() if args.flash: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg", flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") prog.flash(0, "build/gateware/top.bin") exit() platform = netv2.Platform() platform.add_extension(_pcie_analyzer_io) soc = PCIeAnalyzer(platform) builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv") builder.build(run=args.build)
def main(): parser = argparse.ArgumentParser(description="PCIe Screamer Test Gateware") parser.add_argument("--m2", action="store_true", help="use M2 variant of PCIe Screamer") parser.add_argument("--with-analyzer", action="store_true", help="enable Analyzer") parser.add_argument("--with-loopback", action="store_true", help="enable USB Loopback") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") args = parser.parse_args() if args.m2: from platforms.pcie_screamer_m2 import Platform else: from platforms.pcie_screamer import Platform platform = Platform() soc = PCIeScreamer(platform, args.with_analyzer, args.with_loopback) builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv") builder.build(run=args.build) if args.load: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg") prog.load_bitstream("build/gateware/top.bit") if args.flash: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg", flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") prog.flash(0, "build/gateware/top.bin")
def main(): args = sys.argv[1:] load = "load" in args build = not "load" in args if build: with_cpu = "cpu" in args with_emulator = "emulator" in args with_analyzer = "analyzer" in args print("[building]... cpu: {}, emulator: {}, analyzer: {}".format( with_cpu, with_emulator, with_analyzer)) soc = SDSoC(with_cpu, with_emulator, with_analyzer) builder = Builder(soc, output_dir="build", csr_csv="../test/csr.csv") vns = builder.build() soc.do_exit(vns) elif load: print("[loading]...") prog = OpenOCD("board/minispartan6.cfg") prog.load_bitstream("build/gateware/top.bit")
def main(): parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv") parser.add_argument("--build", action="store_true", help="build bitstream") parser.add_argument("--load", action="store_true", help="load bitstream (SRAM)") parser.add_argument("--flash", action="store_true", help="flash bitstream (SPI Flash)") args = parser.parse_args() if args.build: soc = LinuxSoC() builder = Builder(soc, output_dir="build") builder.build() if args.load: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd_xilinx.cfg") prog.load_bitstream("build/gateware/top.bit") if args.flash: flash_regions = { "build/gateware/top.bin": "0x00000000", # FPGA image: automatically loaded at startup "binaries/Image": "0x00400000", # Linux Image: copied to 0xc0000000 by bios "binaries/rootfs.cpio": "0x00800000", # File System: copied to 0xc2000000 by bios "binaries/rv32.dtb": "0x00f00000", # Device tree: copied to 0xc3000000 by bios "emulator/emulator.bin": "0x00f80000", # MM Emulator: copied to 0x20000000 by bios } from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd_xilinx.cfg", flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") for filename, base in flash_regions.items(): base = int(base, 16) print("Flashing {} at 0x{:08x}".format(filename, base)) prog.flash(base, filename)
class XilinxOCDProgrammer(): def __init__(self, soc): openocddir = os.path.join(os.environ["ZTC_TOOLS_DIR"], "share", "openocd") cfg = os.path.join(openocddir, "openocd_xilinx.cfg") device = soc.platform.device.split("-", 1)[0] if device == "xc7a35ticsg324": device = "xc7a35t" flash_proxy = os.path.join("bscan_spi_bitstreams", "bscan_spi_" + device + ".bit") self.prog = OpenOCD(cfg, flash_proxy_basename=flash_proxy) self.prog.set_flash_proxy_dir(openocddir) def load(self, bitstream_file): self.prog.load_bitstream(bitstream_file) def flash(self, regions): for _, item in regions.items(): print("Flashing {} at 0x{:08x}".format(item[0], item[2])) self.prog.flash(item[2], item[0])
def load(self): from litex.build.openocd import OpenOCD prog = OpenOCD("prog/openocd_netv2_rpi.cfg") prog.load_bitstream("build/netv2/gateware/top.bit")
def load(self): from litex.build.openocd import OpenOCD prog = OpenOCD("prog/openocd_xilinx.cfg") prog.load_bitstream("build/arty/gateware/top.bit")
def _prog_fpga_sram(filename): from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg") prog.load_bitstream(filename)