def main():
args = sys.argv[1:]
load = "load" in args
build = (not "load" in args)
if build:
print("[building]...")
plat = arty.Platform()
plat.add_extension(_extension_io)
module = Module()
counter = Signal(32)
module.sync += counter.eq(counter + 1)
serial_pads = plat.request("serial")
io_serial_pads = plat.request("io_serial")
module.comb += [
serial_pads.tx.eq(io_serial_pads.rx),
io_serial_pads.tx.eq(serial_pads.rx),
plat.request("user_led", 0).eq(plat.request("io_leds", 0)),
plat.request("user_led", 1).eq(plat.request("io_leds", 1)),
plat.request("user_led", 2).eq(plat.request("io_leds", 2)),
plat.request("io_rst", 0).eq(plat.request("user_btn", 0)),
]
plat.build(module, source=False)
elif load:
print("[loading]...")
prog = VivadoProgrammer()
prog.load_bitstream("build/top.bit")
def main():
if "load" in sys.argv[1:]:
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream("build/gateware/kc705.bit")
else:
platform = kc705.Platform()
soc = GTXTestSoC(platform)
builder = Builder(soc, output_dir="build", compile_gateware=True)
vns = builder.build(build_name="kc705")
def main():
description = "LiteX-VexRiscv SoC Builder\n\n"
parser = argparse.ArgumentParser(
description=description, formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--build", action="store_true", help="build bitstream")
parser.add_argument("--load",
action="store_true",
help="load bitstream (to SRAM)")
parser.add_argument("--flash",
action="store_true",
help="flash bitstream/images (to SPI Flash)")
args = parser.parse_args()
if args.build:
platform = basys3.Platform()
dut = System(platform)
platform.build(dut,
build_dir="build/sys_accel_simulator_release/gateware")
if args.load:
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream(
"build/sys_accel_simulator_release/gateware/top.bit")
if args.flash:
from litex.build.openocd import OpenOCD
prog = OpenOCD("../prog/openocd_xilinx.cfg",
flash_proxy_basename="../prog/bscan_spi_xc7a35t.bit")
prog.set_flash_proxy_dir(".")
prog.flash(0, "build/sys_accel_simulator_release/gateware/top.bin")
def create_programmer(self):
if self.programmer == "xc3sprog":
return XC3SProg("nexys4")
elif self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported".format(
self.programmer))
def create_programmer(self, programmer="vivado"):
if programmer == "xc3sprog":
return XC3SProg("jtaghs1_fast")
elif programmer == "vivado":
return VivadoProgrammer()
else:
raise ValueError(
"{} programmer is not supported".format(programmer))
def create_programmer(self):
if self.programmer == "xc3sprog":
return XC3SProg("nexys4")
elif self.programmer == "vivado":
return VivadoProgrammer()
else:
raise ValueError("{} programmer is not supported".format(
self.programmer))
def create_programmer(self):
if self.programmer == "xc3sprog":
return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
elif self.programmer == "vivado":
return VivadoProgrammer()
elif self.programmer == "impact":
return iMPACT()
else:
raise ValueError("{} programmer is not supported".format(programmer))
def main():
args = sys.argv[1:]
load = "load" in args
build = not "load" in args
if build:
with_cpu = "cpu" in args
with_emulator = "emulator" in args
with_analyzer = "analyzer" in args
print("[building]... cpu: {}, emulator: {}, analyzer: {}".format(
with_cpu, with_emulator, with_analyzer))
soc = SDSoC(with_cpu, with_emulator, with_analyzer)
builder = Builder(soc, output_dir="build", csr_csv="../test/csr.csv")
vns = builder.build()
soc.do_exit(vns)
elif load:
print("[loading]...")
prog = VivadoProgrammer()
prog.load_bitstream("build/gateware/top.bit")
def create_programmer(self):
if self.programmer == "openocd":
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
return OpenOCD(config="board/digilent_cmod_a7.cfg", flash_proxy_basename=proxy)
elif self.programmer == "vivado":
# n25q32-3.3v-spi-x1_x2_x4
return VivadoProgrammer(flash_part="n25q32-3.3v-spi-x1_x2_x4")
else:
raise ValueError(
"{} programmer is not supported".format(self.programmer))
def create_programmer(self):
if self.programmer == "openocd":
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
return OpenOCD(config="board/numato_mimas_a7.cfg", flash_proxy_basename=proxy)
elif self.programmer == "xc3sprog":
return XC3SProg("nexys4")
elif self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") # FIXME: Spansion S25FL256S
else:
raise ValueError("{} programmer is not supported"
.format(self.programmer))
def create_programmer(self, **kwargs):
# For xc3sprog
# See also http://xc3sprog.sourceforge.net
# get source with: svn checkout https://svn.code.sf.net/p/xc3sprog/code/trunk xc3sprog
if self.programmer == "xc3sprog":
# to program the configuration flash, the FPGA must first be
# programmed with a bitstream which provides a way to foward
# data to flash. This is called a "flash proxy". Flash proxies
# for some parts are already included in xc3sprog. Additional
# ones can be found e.g. https://github.com/quartiq/bscan_spi_bitstreams
# defines which flash proxy bitstream to use for which part
flash_proxy = {
"s7-50": "bscan_spi_xc7s50.bit",
"s7-25": "bscan_spi_xc7s25.bit"
}[self.device_variant]
programmer = XC3SProg("jtaghs1_fast",
flash_proxy_basename=flash_proxy)
# search part where to find proxy bitsreams. If not specified
# defaults to one of:
# "~/.migen", "/usr/local/share/migen", "/usr/share/migen",
# "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs",
# "~/.litex", "/usr/local/share/litex", "/usr/share/litex"
programmer.set_flash_proxy_dir("prog")
return programmer
# For Xilinx Vivado programmer
# Vivado also uses flash proxy bitstreams but they are already shipped
# with Vivado and are used automatically. Flash_part specifies the
# exact part used in the Arty-S7 Rev. E
elif self.programmer == "vivado":
return VivadoProgrammer(flash_part="mt25ql128-spi-x1_x2_x4")
# For OpenOCD
elif self.programmer == "openocd":
bscan_spi = "bscan_spi_xc7s50.bit" \
if "xc7s50" in self.device \
else "bscan_spi_xc7a25.bit"
programmer = OpenOCD("openocd_xilinx.cfg", bscan_spi)
programmer.set_flash_proxy_dir("prog")
return programmer
else:
raise ValueError("{} programmer is not supported".format(
self.programmer))
def load(self):
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer(vivado_path=vivado_path)
prog.load_bitstream("build/nexys_video/gateware/top.bit")
def create_programmer(self):
if self.programmer == "vivado":
return VivadoProgrammer()
else:
raise ValueError(
"{} programmer is not supported".format(programmer))
def load():
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream("build/gateware/ac701.bit")
exit()
def load():
prog = VivadoProgrammer()
prog.load_bitstream("build/gateware/top.bit")
exit()
#!/usr/bin/env python3 from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_pcie_cpri/gateware/top.bit")
#!/usr/bin/env python3 from litex.build.xilinx import VivadoProgrammer prog = VivadoProgrammer() prog.load_bitstream(bitstream_file="build_nexys/gateware/top.bit")
#!/usr/bin/env python3
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream(
bitstream_file="build_pcie_radio/gateware/top.bit",
target="localhost:3121/xilinx_tcf/Digilent/210249810959")
else:
p = os.environ['PLATFORM']
t = os.environ['TARGET']
c = os.environ['CPU']
try:
v = os.environ['CPU_VARIANT']
v = "." + v
except:
v = ""
pass
fname = "build/{p}_{t}_{c}{v}/gateware/top.bit".format(p=p, t=t, c=c, v=v)
print("fname: ", fname)
if prog == 'ise':
from litex.build.xilinx import iMPACT
prog = iMPACT()
elif prog == 'vivado':
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
else:
raise SystemError('Unknown programmer {}'.format(prog))
if not os.path.exists(fname):
raise SystemError('File {} not found'.format(fname))
if not fname.endswith('.bit'):
raise SystemError('Use the .bit file')
prog.load_bitstream(fname)
def load_kcu105():
prog = VivadoProgrammer()
prog.load_bitstream(bitstream_file="build_kcu105/gateware/top.bit")
def create_programmer(self):
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
def create_programmer(self):
if self.programmer == "vivado":
return VivadoProgrammer(flash_part="mx25l6433f-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported".format(
self.programmer))
def load(self):
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream("build/daphne/gateware/top.bit")
def flash():
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer(flash_part="mt25ql256-spi-x1_x2_x4")
prog.flash(0, "build/gateware/ac701.mcs")
exit()
def load_clkgen():
prog = VivadoProgrammer()
prog.load_bitstream(bitstream_file="build_clkgen/gateware/top.bit")
def load_sayma_rtm():
prog = VivadoProgrammer()
prog.load_bitstream(bitstream_file="build_sayma_rtm/gateware/top.bit",
device=1)
def create_programmer(self):
return VivadoProgrammer(flash_part="n25q128a")
def create_programmer(self, name='openocd'):
if name == 'openocd':
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
elif name == 'vivado':
# TODO: some board versions may have s25fl128s
return VivadoProgrammer(flash_part='s25fl256sxxxxxx0-spi-x1_x2_x4')
def load():
prog = VivadoProgrammer()
prog.load_bitstream("build/gateware/kc705.bit")
def create_programmer(self):
return VivadoProgrammer()
#!/usr/bin/env python3
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream("build/gateware/top.bit")
