def __init__(self,
sys_clk_freq=int(200e6),
with_spi_flash=False,
with_hyperram=False,
**kwargs):
platform = efinix_titanium_ti60_f225_dev_kit.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
platform,
sys_clk_freq,
ident="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q64JW
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x",
module=W25Q64JW(Codes.READ_1_1_1),
with_master=True)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram"),
latency=7)
self.bus.add_slave("main_ram",
slave=self.hyperram.bus,
region=SoCRegion(origin=0x40000000,
size=32 * 1024 * 1024))
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = mega65.Platform()
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident="MEGA65", ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x10000,
**kwargs)
# can we just use the clock without PLL ?
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.counter = counter = Signal(32)
self.sync += counter.eq(counter + 1)
#
led_red = platform.request("user_led", 0)
self.comb += led_red.eq(counter[23])
# led_green = platform.request("user_led_green")
# self.comb += led_green.eq(counter[25])
# hyperram_pads = platform.request("hyperram")
# self.submodules.hyperram = HyperRAM(hyperram_pads)
# self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
# self.add_memory_region("hyperram", self.mem_map["hyperram"] | self.shadow_base, 8*1024*1024)
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, **kwargs):
platform = c10lprefkit.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=MT48LC16M16(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self,
sys_clk_freq=int(100e6),
with_led_chaser=True,
**kwargs):
platform = trenz_te0725.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trenz TE0725 Board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Use HyperRAM generic PHY as SRAM ---------------------------------------------------------
size = int((64 * 1024 * 1024) / 8)
hr_pads = platform.request("hyperram", 0)
self.submodules.hyperram = HyperRAM(hr_pads)
self.bus.add_slave("hyperram",
slave=self.hyperram.bus,
region=SoCRegion(origin=0x20000000, size=size))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(50e6),
x5_clk_freq=None,
toolchain="trellis",
**kwargs):
platform = ecp5_evn.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_main_ram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
self.submodules.crg = crg
# HyperRam --------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = c10lprefkit.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]),
self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC16M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def test_hyperram_read(self):
def fpga_gen(dut):
dat = yield from dut.bus.read(0x1234)
self.assertEqual(dat, 0xdeadbeef)
dat = yield from dut.bus.read(0x1235)
self.assertEqual(dat, 0xcafefade)
def hyperram_gen(dut):
clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_"
cs_n = "--________________________________________________________________________________"
dq_oe = "__------------____________________________________________________________________"
dq_o = "00a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
dq_i = "0000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
rwds_oe = "__________________________________________________________________________________"
for i in range(3):
yield
for i in range(len(clk)):
yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
yield
dut = HyperRAM(HyperRamPads())
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def test_hyperram_write(self):
def fpga_gen(dut):
yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
yield
def hyperram_gen(dut):
clk = "___--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
cs_n = "--________________________________________________________________------"
dq_oe = "__------------____________________________________________--------______"
dq_o = "002000048d000000000000000000000000000000000000000000000000deadbeef000000"
rwds_oe = "__________________________________________________________--------______"
rwds_o = "____________________________________________________________----________"
for i in range(3):
yield
for i in range(len(clk)):
self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
yield
dut = HyperRAM(HyperRamPads())
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant",
with_led_chaser=True, **kwargs):
platform = crosslink_nx_vip.Platform(toolchain=toolchain)
platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
kwargs["integrated_sram_size"] = 0
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Crosslink-NX VIP Input Board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
if hyperram == "none":
# 128KB LRAM (used as SRAM) ------------------------------------------------------------
size = 128*kB
self.submodules.spram = NXLRAM(32, size)
self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(size=size))
else:
# Use HyperRAM generic PHY as SRAM -----------------------------------------------------
size = 8*1024*kB
hr_pads = platform.request("hyperram", int(hyperram))
self.submodules.hyperram = HyperRAM(hr_pads)
self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq = sys_clk_freq)
def __init__(self,
sys_clk_freq=int(50e6),
with_led_chaser=True,
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = c10lprefkit.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on C10 LP RefKit",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=MT48LC16M16(sys_clk_freq, "1:1"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = c10lprefkit.Platform()
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]),
self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"],
8 * 1024 * 1024)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC16M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# create VGA terminal
self.mem_map['terminal'] = 0x50000000
self.submodules.terminal = terminal = Terminal(self.crg.cd_vga.clk)
self.add_wb_slave(mem_decoder(self.mem_map["terminal"]),
self.terminal.bus)
self.add_memory_region("terminal", self.mem_map["terminal"], 0x10000)
# connect VGA pins
vga = platform.request('vga', 0)
self.comb += [
vga.vsync.eq(terminal.vga_vsync),
vga.hsync.eq(terminal.vga_hsync),
vga.red.eq(terminal.red[4:8]),
vga.green.eq(terminal.green[4:8]),
vga.blue.eq(terminal.blue[4:8])
]
def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
with_led_chaser=True, **kwargs):
platform = lpddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on LPDDR4 Test Board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq)
# LDDR4 SDRAM ------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = lpddr4.K7LPDDR4PHY(platform.request("lpddr4"),
iodelay_clk_freq = iodelay_clk_freq,
sys_clk_freq = sys_clk_freq,
)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT53E256M16D1(sys_clk_freq, "1:8"),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = 256,
)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
# SD Card ----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard()
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
rx_delay = 0.8e-9,
)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone("serial", baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self,
sys_clk_freq=int(27e6),
with_hyperram=False,
with_led_chaser=True,
with_video_terminal=True,
**kwargs):
platform = tang_nano_4k.Platform()
if "cpu_type" in kwargs and kwargs["cpu_type"] == "gowin_emcu":
kwargs["with_uart"] = False # CPU has own UART
kwargs[
"integrated_sram_size"] = 0 # SRAM is directly attached to CPU
kwargs[
"integrated_rom_size"] = 0 # boot flash directly attached to CPU
else:
# Disable Integrated ROM
kwargs["integrated_rom_size"] = 0
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Tang Nano 4K",
**kwargs)
if self.cpu_type == 'vexriscv':
assert self.cpu_variant == 'minimal', 'use --cpu-variant=minimal to fit into number of BSRAMs'
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_video_pll=with_video_terminal)
if self.cpu_type == "gowin_emcu":
self.cpu.connect_uart(platform.request("serial"))
self.bus.add_region(
"sram", SoCRegion(origin=self.cpu.mem_map["sram"],
size=16 * kB))
self.bus.add_region(
"rom",
SoCRegion(origin=self.cpu.mem_map["rom"],
size=32 * kB,
linker=True))
else:
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q32
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x",
module=W25Q32(Codes.READ_1_1_1),
with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.bus.regions["spiflash"].origin,
size=32 * kB,
linker=True))
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
class HyperRAMPads:
def __init__(self):
self.clk = Signal()
self.rst_n = platform.request("O_hpram_reset_n")
self.dq = platform.request("IO_hpram_dq")
self.cs_n = platform.request("O_hpram_cs_n")
self.rwds = platform.request("IO_hpram_rwds")
hyperram_pads = HyperRAMPads()
self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
self.comb += platform.request("O_hpram_ck_n").eq(
~hyperram_pads.clk)
self.submodules.hyperram = HyperRAM(hyperram_pads)
self.bus.add_slave("main_ram",
slave=self.hyperram.bus,
region=SoCRegion(origin=0x40000000,
size=8 * mB))
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"),
clock_domain="hdmi")
self.add_video_colorbars(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="hdmi")
#self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") # FIXME: Free up BRAMs.
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(27e6),
bios_flash_offset=0x0,
with_led_chaser=True,
**kwargs):
platform = tang_nano_9k.Platform()
# Disable Integrated ROM
kwargs["integrated_rom_size"] = 0
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Tang Nano 9K",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q32
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x",
module=W25Q32(Codes.READ_1_1_1),
with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.bus.regions["spiflash"].origin +
bios_flash_offset,
size=64 * kB,
linker=True))
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# HyperRAM ---------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
# TODO: Use second 32Mbit PSRAM chip.
dq = platform.request("IO_psram_dq")
rwds = platform.request("IO_psram_rwds")
reset_n = platform.request("O_psram_reset_n")
cs_n = platform.request("O_psram_cs_n")
ck = platform.request("O_psram_ck")
ck_n = platform.request("O_psram_ck_n")
class HyperRAMPads:
def __init__(self, n):
self.clk = Signal()
self.rst_n = reset_n[n]
self.dq = dq[8 * n:8 * (n + 1)]
self.cs_n = cs_n[n]
self.rwds = rwds[n]
hyperram_pads = HyperRAMPads(0)
self.comb += ck[0].eq(hyperram_pads.clk)
self.comb += ck_n[0].eq(~hyperram_pads.clk)
self.submodules.hyperram = HyperRAM(hyperram_pads)
self.bus.add_slave("main_ram",
slave=self.hyperram.bus,
region=SoCRegion(
origin=self.mem_map["main_ram"],
size=4 * mB))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
*,
sys_clk_freq=int(100e6),
iodelay_clk_freq=200e6,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_hyperram=False,
with_sdcard=False,
with_jtagbone=True,
with_uartbone=False,
with_led_chaser=True,
eth_reset_time,
**kwargs):
platform = datacenter_ddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on data center test board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
iodelay_clk_freq=iodelay_clk_freq)
# DDR4 SDRAM RDIMM -------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = A7DDRPHY(
platform.request("ddr4"),
memtype="DDR4",
iodelay_clk_freq=iodelay_clk_freq,
sys_clk_freq=sys_clk_freq,
is_rdimm=True,
)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=256,
size=0x40000000,
)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.bus.add_slave("hyperram",
slave=self.hyperram.bus,
region=SoCRegion(origin=0x20000000,
size=8 * 1024 * 1024))
# SD Card ----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard()
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0.8e-9,
hw_reset_cycles=math.ceil(
float(eth_reset_time) * self.sys_clk_freq))
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone("serial", baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# System I2C (behing multiplexer) ----------------------------------------------------------
i2c_pads = platform.request('i2c')
self.submodules.i2c = I2CMaster(i2c_pads)
def test_hyperram_syntax(self):
pads = Record([("clk", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
hyperram = HyperRAM(pads)
pads = Record([("clk_p", 1), ("clk_n", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
hyperram = HyperRAM(pads)