def __init__(self, platform, **kwargs):
clk_freq = 100 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
cpu_type=None,
l2_size=32,
with_uart=False,
with_timer=False)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# uart
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led", i).eq(self.io.output[i])
except:
pass
counter = Signal(16)
self.sync += counter.eq(counter + 1)
toto = Signal()
self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
def __init__(self,
platform,
clk_freq=166 * 1000000,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteEth Base Design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
# ethernet PHY and UDP/IP stack
self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"),
clk_freq=clk_freq)
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address,
convert_ip(ip_address),
clk_freq)
if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.specials += [
Keep(self.crg.cd_sys.clk),
Keep(self.phy.crg.cd_eth_rx.clk),
Keep(self.phy.crg.cd_eth_tx.clk)
]
platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
""")
def __init__(self,
platform,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
clk_freq = int(1e9 / platform.default_clk_period)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Daisho USB3.0 Test Design",
with_timer=False)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# uart <--> wishbone
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# ethernet PHY and UDP/IP stack
self.submodules.eth_phy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"),
clk_freq=clk_freq)
self.submodules.eth_core = LiteEthUDPIPCore(self.eth_phy, mac_address,
convert_ip(ip_address),
clk_freq)
# ethernet <--> wishbone
self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.crg.cd_sys.clk.attr.add("keep")
self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep")
self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 6.0)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
8.0)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
8.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
def __init__(self, platform, revision="sata_gen3", trx_dw=16):
clk_freq = 200 * 1000000
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata", 0),
revision, clk_freq, trx_dw)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
# Status Leds
self.submodules.leds = StatusLeds(platform, self.sata_phy)
self.specials += [
Keep(ClockSignal("sata_rx")),
Keep(ClockSignal("sata_tx"))
]
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
create_clock -name sata_rx_clk -period {sata_clk_period} [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period {sata_clk_period} [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="3.3" if trx_dw == 16 else "6.6"))
def __init__(self, platform, with_uart_bridge=True):
clk_freq = 125 * 1000000
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
shadow_base=0x00000000,
csr_data_width=32,
with_uart=False,
ident="LitePCIe example design",
with_timer=False)
self.submodules.crg = _CRG(platform)
# PCIe endpoint
self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
with_reordering=True)
# PCIe Wishbone bridge
self.add_cpu_or_bridge(
LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# PCIe DMA
self.submodules.dma = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_loopback=True)
self.dma.source.connect(self.dma.sink)
if with_uart_bridge:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
# MSI
self.submodules.msi = LitePCIeMSI()
self.comb += self.msi.source.connect(self.pcie_phy.interrupt)
self.interrupts = {
"dma_writer": self.dma.writer.irq,
"dma_reader": self.dma.reader.irq
}
for k, v in sorted(self.interrupts.items()):
self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v)
def __init__(self, platform, clk_freq=100 * 1000000):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.bus = platform.request("bus")
self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
def __init__(self, platform, revision="sata_gen3", trx_dw=16, nphys=4):
self.nphys = nphys
clk_freq = 200 * 1000000
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHYs
self.sata_phys = []
for i in range(self.nphys):
sata_phy = LiteSATAPHY(
platform.device,
platform.request("sata_clocks")
if i == 0 else self.sata_phys[0].crg.refclk,
platform.request("sata", i), revision, clk_freq, trx_dw)
sata_phy = ClockDomainsRenamer({
"sata_rx":
"sata_rx{}".format(str(i)),
"sata_tx":
"sata_tx{}".format(str(i))
})(sata_phy)
setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
self.sata_phys.append(sata_phy)
# SATA Cores
self.sata_cores = []
for i in range(self.nphys):
sata_core = LiteSATACore(self.sata_phys[i])
setattr(self.submodules, "sata_core{}".format(str(i)), sata_core)
self.sata_cores.append(sata_core)
# SATA Frontend
self.submodules.sata_mirroring = LiteSATAMirroring(self.sata_cores)
self.sata_crossbars = []
for i in range(self.nphys):
sata_crossbar = LiteSATACrossbar(self.sata_mirroring.ports[i])
setattr(self.submodules, "sata_crossbar{}".format(str(i)),
sata_crossbar)
self.sata_crossbars.append(sata_crossbar)
# SATA Application
self.sata_bists = []
for i in range(self.nphys):
sata_bist = LiteSATABIST(self.sata_crossbars[i], with_csr=True)
setattr(self.submodules, "sata_bist{}".format(str(i)), sata_bist)
self.sata_bists.append(sata_bist)
# Status Leds
self.submodules.status_leds = StatusLeds(platform, self.sata_phys)
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
""")
for i in range(len(self.sata_phys)):
self.specials += [
Keep(ClockSignal("sata_rx{}".format(str(i)))),
Keep(ClockSignal("sata_tx{}".format(str(i))))
]
platform.add_platform_command("""
create_clock -name {sata_rx_clk} -period {sata_clk_period} [get_nets {sata_rx_clk}]
create_clock -name {sata_tx_clk} -period {sata_clk_period} [get_nets {sata_tx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
sata_tx_clk="sata_tx{}_clk".format(str(i)),
sata_clk_period="3.3" if trx_dw == 16 else "6.6"))
def __init__(self, platform,
with_sdram_bist=True, bist_async=True, bist_random=False):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type=None,
l2_size=32,
csr_data_width=32,
with_uart=False,
with_timer=False)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random)
# uart
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# logic analyzer
analyzer_signals = [Signal(2)]
if False:
analyzer_signals = [
generator_user_port.cmd.valid,
generator_user_port.cmd.ready,
generator_user_port.cmd.we,
generator_user_port.cmd.adr,
generator_user_port.wdata.valid,
generator_user_port.wdata.ready,
generator_user_port.wdata.we,
self.generator.start.re,
self.checker.start.re
]
if False:
gen_data = Signal(32)
read_data = Signal(32)
self.comb += [
gen_data.eq(self.checker.core.gen.o),
read_data.eq(checker_user_port.rdata.data)
]
analyzer_signals = [
checker_user_port.cmd.valid,
checker_user_port.cmd.ready,
checker_user_port.cmd.we,
checker_user_port.cmd.adr,
checker_user_port.rdata.valid,
checker_user_port.rdata.ready,
self.generator.start.re,
self.checker.start.re,
gen_data,
read_data,
self.checker.core.errors
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)