def add_uart(self, name, baudrate=115200): from litex.soc.cores import uart if name in ["stub", "stream"]: self.submodules.uart = uart.UART() if name == "stub": self.comb += self.uart.sink.ready.eq(1) elif name == "bridge": self.submodules.uart = uart.UARTWishboneBridge( pads = self.platform.request("serial"), clk_freq = self.sys_clk_freq, baudrate = baudrate) self.bus.add_master(name="uart_bridge", master=self.uart.wishbone) elif name == "crossover": self.submodules.uart = uart.UARTCrossover() else: if name == "jtag_atlantic": from litex.soc.cores.jtag import JTAGAtlantic self.submodules.uart_phy = JTAGAtlantic() elif name == "jtag_uart": from litex.soc.cores.jtag import JTAGPHY self.submodules.uart_phy = JTAGPHY(device=self.platform.device) else: self.submodules.uart_phy = uart.UARTPHY( pads = self.platform.request(name), clk_freq = self.sys_clk_freq, baudrate = baudrate) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) self.csr.add("uart_phy", use_loc_if_exists=True) self.csr.add("uart", use_loc_if_exists=True) self.irq.add("uart", use_loc_if_exists=True)
def __init__(self, **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, ident="LiteX simulation example design", with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) if not self.integrated_main_ram_size: sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
def __init__(self, with_ethernet=False): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0x8000, integrated_main_ram_size=0x02000000, # 32MB integrated_main_ram_init=get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000" }, "little")) self.add_constant("SIM", None) # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, platform, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 2048 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size'] = 16384 if 'integrated_main_ram_size' not in kwargs: kwargs['integrated_main_ram_size'] = 0 clk_freq = sys_clk_freq self.submodules.crg = _CRG(platform) # no londer neaded? #platform = cycloneIV_generic.Platform() # spiflash being tested #kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size SoCCore.__init__(self, platform, clk_freq, **kwargs) self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) self.submodules.uart_phy = uart.RS232PHY(platform.request('serial', 1), clk_freq, baudrate=115200) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) self.submodules.i2c = bitbang.I2CMaster(platform.request('i2c')) self.submodules.gpio = gpio.GPIOInOut(platform.request('gpio', 0), platform.request('gpio', 1))
def __init__(self, clk_freq, baud_rate): self.tx = Signal() self.rx = Signal() self.tx_signals = [] self.rx_signals = [] self.submodules.phy = uart.RS232PHY(self, clk_freq, baud_rate) self.submodules.uart = uart.UART(self.phy)
def __init__(self, **kwargs): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0xC000, integrated_main_ram_size=0x02000000, # 32MB **kwargs) # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # Integrate Adder8 self.submodules.adder8 = Adder8() self.add_csr("adder8", 10, allow_user_defined=True) # Integrate CAN # self.submodules.can_ctrl = can_ctrl = SJA1000(platform.request("canif", 0)) # self.add_csr("can_ctrl", 11, allow_user_defined=True) # self.add_interrupt("can_ctrl", 6, allow_user_defined=True) # self.register_mem("can_ctrl", 0x30000000, can_ctrl.bus, 512) # can_ctrl.add_source(platform) # platform.add_verilog_include_path("periphs/verilog/can") # Integrate SPI master self.submodules.spi_master = spi_master = SpiMaster( self.platform.request("spi", 0)) self.add_csr("spi_master", 11, allow_user_defined=True) self.add_interrupt("spi_master", 6, allow_user_defined=True) self.register_mem("spi_master", 0x30000000, spi_master.bus, 32) spi_master.add_source(self.platform) platform.add_verilog_include_path("periphs/verilog/spi")
def __init__(self, platform, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x10000) if kwargs.get('cpu_type', None) == 'mor1kx': dict_set_max(kwargs, 'integrated_rom_size', 0x10000) else: dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) dict_set_max(kwargs, 'firmware_ram_size', 0x10000) if 'firmware_filename' not in kwargs: kwargs[ 'firmware_filename'] = "build/sim_{}_{}/software/firmware/firmware.fbi".format( self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32')) clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM( firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.flash_boot_address = self.mem_map["firmware_ram"] define_flash_constants(self) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings(memtype="SDR", dfi_databits=1 * 32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1)
def __init__(self, firmware_ram_size=0x10000, firmware_filename="firmware/firmware.bin", **kwargs): platform = sim.Platform() SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, integrated_sram_size=0x8000, with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # firmware self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) # sdram sdram_module = IS42S16160(self.clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*32, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) controller_settings = ControllerSettings(with_refresh=False) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 1024) self.add_constant("MEMTEST_ADDR_SIZE", 1024) self.add_constant("SIMULATION", 1) self.submodules.video_out = VideoOutCore(self.sdram.crossbar.get_port()) self.submodules.vga = VGAModel(platform.request("vga")) self.comb += self.video_out.source.connect(self.vga.sink)
def __init__(self, sys_clk_freq=int(100e6)): platform = nexys4.Platform() # SoCCore ----------------------------------_----------------------------------------------- SoCCore.__init__( self, platform, sys_clk_freq, cpu_type="vexriscv", # or picorv32 ident="LiteX SoC on Nexys4", ident_version=True, integrated_rom_size=0x8000, integrated_main_ram_size=0x4000, ) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset")) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # Uart Adicional # Classical UART. En /litex/soc/integration/soc.py self.submodules.uart1_phy = uart.UARTPHY( pads=platform.request("uart1"), clk_freq=self.sys_clk_freq, baudrate=9600 ) # crea un objeto uart RS232PHY. Este despues se pasa a UART self.submodules.uart1 = ResetInserter()( uart.UART( self.uart1_phy, #paso a UART. ResetInserter no idea tx_fifo_depth=16, rx_fifo_depth=16)) self.csr.add("uart1_phy", use_loc_if_exists=True) self.csr.add("uart1", use_loc_if_exists=True) if hasattr(self.cpu, "interrupt"): self.irq.add("uart1", use_loc_if_exists=True) else: self.add_constant("UART_POLLING")
def __init__(self, platform, cpu, sim: bool, **kwargs): sys_clk_freq = int(1e9 / platform.default_clk_period) kwargs['with_uart'] = not sim SoCCore.__init__(self, platform, cpu_type=cpu.name, clk_freq=sys_clk_freq, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.gpio_led = gpio.GPIOOut(platform.request("user_led")) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map['main_ram']) if sim: # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy, tx_fifo_depth=kwargs["uart_fifo_depth"], rx_fifo_depth=kwargs["uart_fifo_depth"]) self.add_csr("uart") self.add_interrupt("uart")
def __init__(self, **kwargs): platform = Platform() sys_clk_freq = int(1e6) SoCCore.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, integrated_rom_size=0x8000, integrated_main_ram_size=0x02000000, # 32MB integrated_main_ram_init=get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000" }, "little"), **kwargs) self.cpu.use_external_variant("VexRiscv.v") # supervisor self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # crg self.submodules.crg = CRG(platform.request("sys_clk")) # machine mode emulator ram emulator_rom = get_mem_data("emulator/emulator.bin", "little") self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # serial self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True)
def main(): parser = argparse.ArgumentParser(description=__doc__) builder_args(parser) MySoc.basesoc_args(parser) parser.add_argument("--trace", action="store_true", help="enable VCD tracing") parser.add_argument("--rom-init", default=None, help="rom_init file") parser.set_defaults( integrated_rom_size=0x8000, integrated_main_ram_size=0x8000, # integrated_sram_size=0, # Litex will complain if 0! cpu_type="vexriscv", platform="cmod_a7_sim", clk_freq=int(1e6), with_uart=False # We will add our own mock uart ) args = parser.parse_args() soc_kwargs = vars(args) if args.rom_init: soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init) soc = MySoc(crg=CRG, **soc_kwargs) # Push in a fake uart soc.submodules.uart_phy = uart.RS232PHYModel(soc.platform.request("serial")) soc.submodules.uart = uart.UART(soc.uart_phy) sim_config = SimConfig(default_clk="sys_clk") # sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"}) sim_config.add_module("serial2console", "serial") # sim_config.add_module("serial2tcp", "serial", args={"port": 55555}) # now you can do these 2 things to get a terminal # telnet localhost 55555 # litex_term socket://localhost:55555 # soc.add_constant("TFTP_SERVER_PORT", int(tftp_port)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=False, sim_config=sim_config, trace=args.trace)
def __init__(self, platform, clk_freq, # CPU parameters cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, # MEM MAP parameters shadow_base=0x80000000, # ROM parameters integrated_rom_size=0, integrated_rom_init=[], # SRAM parameters integrated_sram_size=4096, integrated_sram_init=[], # MAIN_RAM parameters integrated_main_ram_size=0, integrated_main_ram_init=[], # CSR parameters csr_data_width=8, csr_address_width=14, # Identifier parameters ident="", ident_version=False, # UART parameters with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False, # Timer parameters with_timer=True, # Controller parameters with_ctrl=True, # Wishbone parameters wishbone_timeout_cycles=1e6): self.platform = platform self.clk_freq = clk_freq # config dictionary (store all SoC's parameters to be exported to software) self.config = dict() # SoC's register/interrupt/memory mappings (default or user defined + dynamically allocateds) self.soc_csr_map = {} self.soc_interrupt_map = {} self.soc_mem_map = self.mem_map # Regions / Constants lists self._memory_regions = [] # (name, origin, length) self._csr_regions = [] # (name, origin, busword, csr_list/Memory) self._constants = [] # (name, value) # Wishbone masters/slaves lists self._wb_masters = [] self._wb_slaves = [] # CSR masters list self._csr_masters = [] # Parameters managment --------------------------------------------------------------------- # FIXME: RocketChip reserves the first 256Mbytes for internal use # remap rom to 0x10000000, sram to 0x20000000 if cpu_type == "rocket": self.soc_mem_map["rom"] = 0x10000000 self.soc_mem_map["sram"] = 0x20000000 if cpu_type == "None": cpu_type = None self.cpu_type = cpu_type # Support the old style which used underscore for separator if cpu_variant is None: cpu_variant = "standard" cpu_variant = cpu_variant.replace('_', '+') # Check for valid CPU variants. cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+') for key, values in CPU_VARIANTS.items(): if cpu_variant_processor not in [key,]+values: continue self.cpu_variant = key break else: raise InvalidCPUVariantError(cpu_variant) # Check for valid CPU extensions. for ext in sorted(cpu_variant_ext): if ext not in CPU_VARIANTS_EXTENSIONS: raise InvalidCPUExtensionError(cpu_variant) self.cpu_variant += "+"+ext if integrated_rom_size: cpu_reset_address = self.soc_mem_map["rom"] self.cpu_reset_address = cpu_reset_address self.config["CPU_RESET_ADDR"] = self.cpu_reset_address self.shadow_base = shadow_base self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width self.with_ctrl = with_ctrl self.with_uart = with_uart self.uart_baudrate = uart_baudrate self.wishbone_timeout_cycles = wishbone_timeout_cycles # Modules instances ------------------------------------------------------------------------ # Add user's CSRs (needs to be done before the first dynamic allocation) for _name, _id in self.csr_map.items(): self.add_csr(_name, _id) # Add SoCController if with_ctrl: self.submodules.ctrl = SoCController() self.add_csr("ctrl", allow_user_defined=True) # Add CPU self.config["CPU_TYPE"] = str(cpu_type).upper() if cpu_type is not None: # CPU selection / instance if cpu_type == "lm32": self.add_cpu(lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "mor1kx" or cpu_type == "or1k": if cpu_type == "or1k": deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"") self.add_cpu(mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "picorv32": self.add_cpu(picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "vexriscv": self.add_cpu(vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "minerva": self.add_cpu(minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "rocket": self.add_cpu(rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant)) else: raise ValueError("Unsupported CPU type: {}".format(cpu_type)) # Add Instruction/Data buses as Wisbone masters self.add_wb_master(self.cpu.ibus) self.add_wb_master(self.cpu.dbus) # Add CPU CSR (dynamic) self.add_csr("cpu", allow_user_defined=True) # Add CPU reserved interrupts for _name, _id in self.cpu.reserved_interrupts.items(): self.add_interrupt(_name, _id) # Allow SoCController to reset the CPU if with_ctrl: self.comb += self.cpu.reset.eq(self.ctrl.reset) # Add user's interrupts (needs to be done after CPU reserved interrupts are allocated) for _name, _id in self.interrupt_map.items(): self.add_interrupt(_name, _id) # Add integrated ROM if integrated_rom_size: self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init) self.register_rom(self.rom.bus, integrated_rom_size) # Add integrated SRAM if integrated_sram_size: self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init) self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size) # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available) if integrated_main_ram_size: self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init) self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) # Add Wishbone to CSR bridge self.submodules.wishbone2csr = wishbone2csr.WB2CSR( bus_csr=csr_bus.Interface(csr_data_width, csr_address_width)) self.add_csr_master(self.wishbone2csr.csr) self.config["CSR_DATA_WIDTH"] = csr_data_width self.add_constant("CSR_DATA_WIDTH", csr_data_width) self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone) # Add UART if with_uart: if uart_stub: self.submodules.uart = uart.UARTStub() else: self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) self.add_csr("uart_phy", allow_user_defined=True) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # Add Identifier if ident: if ident_version: ident = ident + " " + version() self.submodules.identifier = identifier.Identifier(ident) self.add_csr("identifier_mem", allow_user_defined=True) self.config["CLOCK_FREQUENCY"] = int(clk_freq) self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq)) # Add Timer if with_timer: self.submodules.timer0 = timer.Timer() self.add_csr("timer0", allow_user_defined=True) self.add_interrupt("timer0", allow_user_defined=True)
def __init__(self, platform, use_dsp=False, placer="heap", output_dir="build", pnr_seed=0, sim=False, hard_i2c=False, **kwargs): self.output_dir = output_dir # Core ------------------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, with_uart=False, cpu_reset_address=self.mem_map["spiflash"] + GATEWARE_SIZE, csr_data_width=32, **kwargs) self.cpu.use_external_variant( "deps/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_MinPlus.v" ) self.submodules.crg = platform.CRG(platform) self.add_csr("crg") # Version ---------------------------------------------------------------------------------------- self.submodules.git = GitInfo() self.add_csr("git") # Power management ------------------------------------------------------------------------------- # Betrusted Power management interface self.submodules.power = BtPower(platform.request("power")) self.add_csr("power") # Keyboard power-on + debug mux ------------------------------------------------------------------ # Use to debug bootstrapping issues, avoid internal state on SoC messing with access to UART pads. # Prevents sleep/wake from working due to loss of modal pinmux. debugonly = False if debugonly: self.submodules.uart_phy = uart.UARTPHY( pads=platform.request("serial"), clk_freq=clk_freq, baudrate=115200) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy, tx_fifo_depth=256, rx_fifo_depth=16)) self.add_csr("uart_phy") self.add_csr("uart") self.add_interrupt("uart") else: serialpads = platform.request("serial") dbguart_tx = Signal() dbguart_rx = Signal() dbgpads = Record([('rx', 1), ('tx', 1)], name="serial") dbgpads.rx = dbguart_rx dbgpads.tx = dbguart_tx # serialpad RX needs to drive a scan signal so we can detect it on the other side of the matrix keycol0_ts = TSTriple(1) self.specials += keycol0_ts.get_tristate(serialpads.rx) #self.comb += serialpads.rx.eq(1) self.comb += dbgpads.rx.eq(keycol0_ts.i) self.comb += self.power.mon1.eq(platform.request("up5k_keyrow1")) self.comb += self.power.mon0.eq(platform.request("up5k_keyrow0")) # serialpad TX is what we use to test for keyboard hit to power on the SOC # only allow test keyboard hit patterns when the SOC is powered off self.comb += [ If(self.power.stats.fields.state, serialpads.tx.eq(dbgpads.tx), keycol0_ts.oe.eq(0)).Else( serialpads.tx.eq(self.power.power.fields.kbddrive), keycol0_ts.oe.eq(1)) ] self.comb += keycol0_ts.o.eq(1) # drive a '1' for scan # Uart block ------------------------------------------------------------------------------------ self.submodules.uart_phy = uart.UARTPHY(pads=dbgpads, clk_freq=clk_freq, baudrate=115200) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy, tx_fifo_depth=256, rx_fifo_depth=16)) self.add_csr("uart_phy") self.add_csr("uart") self.add_interrupt("uart") # RAM/ROM/reset cluster -------------------------------------------------------------------------- spram_size = 128 * 1024 self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size) self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size) # Add a simple bit-banged SPI Flash module spi_pads = platform.request("spiflash") self.submodules.picorvspi = PicoRVSpi(platform, spi_pads) self.register_mem("spiflash", self.mem_map["spiflash"], self.picorvspi.bus, size=SPI_FLASH_SIZE) self.add_csr("picorvspi") # I2C -------------------------------------------------------------------------------------------- if hard_i2c: self.submodules.i2c = HardI2C(platform, platform.request("i2c", 0)) self.add_wb_slave(self.mem_map["i2c"], self.i2c.bus, 16 * 4) self.add_memory_region("i2c", self.mem_map["i2c"], 16 * 4, type='io') self.add_csr("i2c") self.add_interrupt("i2c") else: self.submodules.i2c = RtlI2C(platform, platform.request("i2c", 0)) self.add_csr("i2c") self.add_interrupt("i2c") # High-resolution tick timer --------------------------------------------------------------------- self.submodules.ticktimer = TickTimer(1000, clk_freq, bits=40) self.add_csr("ticktimer") self.add_interrupt("ticktimer") # COM port (spi peripheral to Artix) ------------------------------------------------------------------ self.submodules.com = SpiFifoPeripheral(platform.request("com"), pipeline_cipo=True) self.add_wb_slave(self.mem_map["com"], self.com.bus, 4) self.add_memory_region("com", self.mem_map["com"], 4, type='io') self.add_csr("com") self.comb += self.com.oe.eq( self.power.stats.fields.state ) # only drive to FPGA when it's powered up # SPI port to wifi (controller) ------------------------------------------------------------------ self.submodules.wifi = ClockDomainsRenamer({'spi': 'sys'})( SpiController( platform.request("wifi"), gpio_cs=True)) # control CS with GPIO per wf200 API spec self.add_csr("wifi") self.add_interrupt("wifi") #### Platform config & build below --------------------------------------------------------------- # Override default LiteX's yosys/build templates assert hasattr(platform.toolchain, "yosys_template") assert hasattr(platform.toolchain, "build_template") platform.toolchain.yosys_template = [ "{read_files}", "attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0", "synth_ice40 -json {build_name}.json -top {build_name}", ] platform.toolchain.build_template = [ "yosys -q -l {build_name}.rpt {build_name}.ys", "nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \ --pre-pack {build_name}_pre_pack.py --{architecture} --package {package}", "icepack {build_name}.txt {build_name}.bin" ] # Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command. # The "-reult" adds an additional LUT pass to pack more stuff in, # and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a # Clock Enable signal for a LUT that has fewer than 4 flip-flops. # This increases density, and lets us use the FPGA more efficiently. platform.toolchain.yosys_template[ 2] += " -relut -abc2 -dffe_min_ce_use 4 -relut" if use_dsp: platform.toolchain.yosys_template[2] += " -dsp" # Disable final deep-sleep power down so firmware words are loaded # onto softcore's address bus. platform.toolchain.build_template[ 2] = "icepack -s {build_name}.txt {build_name}.bin" # Allow us to set the nextpnr seed platform.toolchain.build_template[1] += " --seed " + str(pnr_seed) if placer is not None: platform.toolchain.build_template[1] += " --placer {}".format( placer) # Allow loops for RNG placement platform.toolchain.build_template[1] += " --ignore-loops" if sim: class _WishboneBridge(Module): def __init__(self, interface): self.wishbone = interface self.add_cpu(_WishboneBridge(self.platform.request("wishbone"))) self.add_wb_master(self.cpu.wishbone)
def __init__(self): platform = tarjeta.Platform() ## add source verilog platform.add_source("module/verilog/camara.v") platform.add_source("module/verilog/Infrarrojo/modulo_ir.v") platform.add_source("module/verilog/PWM/BloquePWM.v") platform.add_source("module/verilog/PWM/PWM.v") platform.add_source("module/verilog/PWM/MaquinaEstadosPWM.v") platform.add_source("module/verilog/PWM/DivFreqPWM.v") platform.add_source( "module/verilog/Ultrasonido(NexysA7)/bloqueultrasonido.v") platform.add_source("module/verilog/Ultrasonido(NexysA7)/contador.v") platform.add_source("module/verilog/Ultrasonido(NexysA7)/divisor.v") platform.add_source( "module/verilog/Ultrasonido(NexysA7)/divisorfrec.v") platform.add_source( "module/verilog/Ultrasonido(NexysA7)/divisorfrecd.v") platform.add_source( "module/verilog/Ultrasonido(NexysA7)/divisorfrecgen.v") platform.add_source( "module/verilog/Ultrasonido(NexysA7)/divisorfrecme.v") platform.add_source("module/verilog/Ultrasonido(NexysA7)/genpulsos.v") platform.add_source( "module/verilog/Ultrasonido(NexysA7)/maquinadeestados.v") platform.add_source( "module/verilog/Ultrasonido(NexysA7)/meultrasonido.v") platform.add_source( "module/verilog/Ultrasonido(NexysA7)/ultrasonido.v") clk_freq = 100e6 # SoC with CPU SoCCore.__init__( self, platform, cpu_type="picorv32", # cpu_type="vexriscv", clk_freq=100e6, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk"), ~platform.request("cpu_reset")) # Leds SoCCore.add_csr(self, "leds") user_leds = Cat(*[platform.request("led", i) for i in range(10)]) self.submodules.leds = gpio.GPIOOut(user_leds) # Switchs SoCCore.add_csr(self, "switchs") user_switchs = Cat(*[platform.request("sw", i) for i in range(8)]) self.submodules.switchs = gpio.GPIOIn(user_switchs) # Buttons SoCCore.add_csr(self, "buttons") user_buttons = Cat( *[platform.request("btn%c" % c) for c in ['c', 'r', 'l']]) self.submodules.buttons = gpio.GPIOIn(user_buttons) # 7segments Display SoCCore.add_csr(self, "display") display_segments = Cat( *[platform.request("display_segment", i) for i in range(8)]) display_digits = Cat( *[platform.request("display_digit", i) for i in range(8)]) self.submodules.display = sevensegment.SevenSegment( display_segments, display_digits) # RGB leds SoCCore.add_csr(self, "ledRGB_1") self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1)) SoCCore.add_csr(self, "ledRGB_2") self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2)) # VGA SoCCore.add_csr(self, "vga_cntrl") vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)]) vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)]) vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)]) self.submodules.vga_cntrl = vgacontroller.VGAcontroller( platform.request("hsync"), platform.request("vsync"), vga_red, vga_green, vga_blue) #camara """ /* SoCCore.add_csr(self,"camara_cntrl") SoCCore.add_interrupt(self,"camara_cntrl") cam_data_in = Cat(*[platform.request("cam_data_in", i) for i in range(8)]) self.submodules.camara_cntrl = camara.Camara(platform.request("cam_xclk"),platform.request("cam_pclk"),cam_data_in) """ #serialA from litex.soc.cores import uart self.submodules.uart1_phy = uart.UARTPHY( pads=platform.request("uart1"), clk_freq=self.sys_clk_freq, baudrate=9600) self.submodules.uart1 = ResetInserter()(uart.UART(self.uart1_phy, tx_fifo_depth=16, rx_fifo_depth=16)) self.csr.add("uart1_phy", use_loc_if_exists=True) self.csr.add("uart1", use_loc_if_exists=True) if hasattr(self.cpu, "interrupt"): self.irq.add("uart1", use_loc_if_exists=True) else: self.add_constant("UART_POLLING") #Infrarrojo SoCCore.add_csr(self, "infrarrojo_cntrl") self.submodules.infrarrojo_cntrl = infrarrojo.Infrarrojo( platform.request("ir_inout")) #PWM SoCCore.add_csr(self, "pwm_cntrl") self.submodules.pwm_cntrl = pwm.PWM(platform.request("pwm_out")) #Ultrasonido SoCCore.add_csr(self, "ultrasonido") self.submodules.ultrasonido = ultrasonido.Ultrasonido( platform.request("us_trigger"), platform.request("us_echo"))
def __init__(self, platform, clk_freq, # CPU parameters cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, # MEM MAP parameters shadow_base=0x80000000, # ROM parameters integrated_rom_size=0, integrated_rom_init=[], # SRAM parameters integrated_sram_size=4096, integrated_sram_init=[], # MAIN_RAM parameters integrated_main_ram_size=0, integrated_main_ram_init=[], # CSR parameters csr_data_width=8, csr_alignment=32, csr_address_width=14, # Identifier parameters ident="", ident_version=False, # UART parameters with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False, # Timer parameters with_timer=True, # Controller parameters with_ctrl=True, # Wishbone parameters with_wishbone=True, wishbone_timeout_cycles=1e6): self.platform = platform self.clk_freq = clk_freq # config dictionary (store all SoC's parameters to be exported to software) self.config = dict() # SoC's register/interrupt/memory mappings (default or user defined + dynamically allocateds) self.soc_csr_map = {} self.soc_interrupt_map = {} self.soc_mem_map = self.mem_map # Regions / Constants lists self._memory_regions = [] # (name, origin, length) self._csr_regions = [] # (name, origin, busword, csr_list/Memory) self._constants = [] # (name, value) # Wishbone masters/slaves lists self._wb_masters = [] self._wb_slaves = [] # CSR masters list self._csr_masters = [] # Parameters managment --------------------------------------------------------------------- # NOTE: RocketChip reserves the first 256Mbytes for internal use, # so we must change default mem_map; # Also, CSRs *must* be 64-bit aligned. if cpu_type == "rocket": self.soc_mem_map["rom"] = 0x10000000 self.soc_mem_map["sram"] = 0x11000000 self.soc_mem_map["csr"] = 0x12000000 csr_alignment = 64 # Mainline Linux OpenRISC arch code requires Linux kernel to be loaded # at the physical address of 0x0. As we are running Linux from the # MAIN_RAM region - move it to satisfy that requirement. if cpu_type == "mor1kx" and cpu_variant == "linux": self.soc_mem_map["main_ram"] = 0x00000000 self.soc_mem_map["rom"] = 0x10000000 self.soc_mem_map["sram"] = 0x50000000 self.soc_mem_map["csr"] = 0x60000000 if cpu_type == "None": cpu_type = None if not with_wishbone: self.soc_mem_map["csr"] = 0x00000000 self.cpu_type = cpu_type self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant) if integrated_rom_size: cpu_reset_address = self.soc_mem_map["rom"] self.cpu_reset_address = cpu_reset_address self.config["CPU_RESET_ADDR"] = self.cpu_reset_address self.shadow_base = shadow_base self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size assert csr_data_width in [8, 32, 64] assert csr_alignment in [32, 64] assert 2**(csr_address_width + 2) <= 0x1000000 self.csr_data_width = csr_data_width self.csr_alignment = csr_alignment self.csr_address_width = csr_address_width self.with_ctrl = with_ctrl self.with_uart = with_uart self.uart_baudrate = uart_baudrate self.with_wishbone = with_wishbone self.wishbone_timeout_cycles = wishbone_timeout_cycles # Modules instances ------------------------------------------------------------------------ # Add user's CSRs (needs to be done before the first dynamic allocation) for _name, _id in self.csr_map.items(): self.add_csr(_name, _id) # Add SoCController if with_ctrl: self.submodules.ctrl = SoCController() self.add_csr("ctrl", allow_user_defined=True) # Add CPU self.config["CPU_TYPE"] = str(cpu_type).upper() if cpu_type is not None: if cpu_variant is not None: self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper() # CPU selection / instance if cpu_type == "lm32": self.add_cpu(cpu.lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "mor1kx" or cpu_type == "or1k": if cpu_type == "or1k": deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"") self.add_cpu(cpu.mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "picorv32": self.add_cpu(cpu.picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "vexriscv": self.add_cpu(cpu.vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "minerva": self.add_cpu(cpu.minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "rocket": self.add_cpu(cpu.rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant)) else: raise ValueError("Unsupported CPU type: {}".format(cpu_type)) # Add Instruction/Data buses as Wisbone masters self.add_wb_master(self.cpu.ibus) self.add_wb_master(self.cpu.dbus) # Add CPU CSR (dynamic) self.add_csr("cpu", allow_user_defined=True) # Add CPU reserved interrupts for _name, _id in self.cpu.reserved_interrupts.items(): self.add_interrupt(_name, _id) # Allow SoCController to reset the CPU if with_ctrl: self.comb += self.cpu.reset.eq(self.ctrl.reset) # Add user's interrupts (needs to be done after CPU reserved interrupts are allocated) for _name, _id in self.interrupt_map.items(): self.add_interrupt(_name, _id) # Add integrated ROM if integrated_rom_size: self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init) self.register_rom(self.rom.bus, integrated_rom_size) # Add integrated SRAM if integrated_sram_size: self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init) self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size) # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available) if integrated_main_ram_size: self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init) self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) # Add UART if with_uart: if uart_stub: self.submodules.uart = uart.UARTStub() else: if uart_name == "jtag_atlantic": from litex.soc.cores.jtag import JTAGAtlantic self.submodules.uart_phy = JTAGAtlantic() elif uart_name == "jtag_uart": from litex.soc.cores.jtag import JTAGPHY self.submodules.uart_phy = JTAGPHY(device=platform.device) else: self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) self.add_csr("uart_phy", allow_user_defined=True) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # Add Identifier if ident: if ident_version: ident = ident + " " + version() self.submodules.identifier = identifier.Identifier(ident) self.add_csr("identifier_mem", allow_user_defined=True) self.config["CLOCK_FREQUENCY"] = int(clk_freq) # Add Timer if with_timer: self.submodules.timer0 = timer.Timer() self.add_csr("timer0", allow_user_defined=True) self.add_interrupt("timer0", allow_user_defined=True) # Add Wishbone to CSR bridge self.config["CSR_DATA_WIDTH"] = self.csr_data_width self.config["CSR_ALIGNMENT"] = self.csr_alignment if with_wishbone: self.submodules.wishbone2csr = wishbone2csr.WB2CSR( bus_csr=csr_bus.Interface( address_width=self.csr_address_width, data_width=self.csr_data_width)) self.add_csr_master(self.wishbone2csr.csr) self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)
def __init__(self): platform = tarjeta.Platform() ## add source verilog platform.add_source("module/verilog/camara.v") clk_freq = 100e6 # SoC with CPU SoCCore.__init__( self, platform, cpu_type="picorv32", # cpu_type="vexriscv", clk_freq=100e6, integrated_rom_size=0x8000, integrated_main_ram_size=16 * 1024) # Clock Reset Generation self.submodules.crg = CRG(platform.request("clk"), ~platform.request("cpu_reset")) # Leds SoCCore.add_csr(self, "leds") user_leds = Cat(*[platform.request("led", i) for i in range(10)]) self.submodules.leds = gpio.GPIOOut(user_leds) # Switchs SoCCore.add_csr(self, "switchs") user_switchs = Cat(*[platform.request("sw", i) for i in range(8)]) self.submodules.switchs = gpio.GPIOIn(user_switchs) # Buttons SoCCore.add_csr(self, "buttons") user_buttons = Cat( *[platform.request("btn%c" % c) for c in ['c', 'r', 'l']]) self.submodules.buttons = gpio.GPIOIn(user_buttons) # 7segments Display SoCCore.add_csr(self, "display") display_segments = Cat( *[platform.request("display_segment", i) for i in range(8)]) display_digits = Cat( *[platform.request("display_digit", i) for i in range(8)]) self.submodules.display = sevensegment.SevenSegment( display_segments, display_digits) # RGB leds SoCCore.add_csr(self, "ledRGB_1") self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1)) SoCCore.add_csr(self, "ledRGB_2") self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2)) # VGA SoCCore.add_csr(self, "vga_cntrl") vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)]) vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)]) vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)]) self.submodules.vga_cntrl = vgacontroller.VGAcontroller( platform.request("hsync"), platform.request("vsync"), vga_red, vga_green, vga_blue) #camara SoCCore.add_csr(self, "camara_cntrl") SoCCore.add_interrupt(self, "camara_cntrl") cam_data_in = Cat( *[platform.request("cam_data_in", i) for i in range(8)]) self.submodules.camara_cntrl = camara.Camara( platform.request("cam_xclk"), platform.request("cam_pclk"), cam_data_in) #serialA from litex.soc.cores import uart self.submodules.uart1_phy = uart.UARTPHY( pads=platform.request("uart1"), clk_freq=self.sys_clk_freq, baudrate=115200) self.submodules.uart1 = ResetInserter()(uart.UART(self.uart1_phy, tx_fifo_depth=16, rx_fifo_depth=16)) self.csr.add("uart1_phy", use_loc_if_exists=True) self.csr.add("uart1", use_loc_if_exists=True) if hasattr(self.cpu, "interrupt"): self.irq.add("uart1", use_loc_if_exists=True) else: self.add_constant("UART_POLLING")
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart") self.add_interrupt("uart") # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_module = MT48LC16M16(100e6, "1:1") # use 100MHz timings phy_settings = PhySettings(memtype="SDR", databits=32, dfi_databits=16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024) assert not (with_ethernet and with_etherbone ) # FIXME: fix simulator with 2 ethernet interfaces # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({ "eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx" })(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") # Ethernet --------------------------------------------------------------------------------- if with_etherbone: # Ethernet PHY self.submodules.etherbonephy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("etherbonephy") # Ethernet MAC etherbonecore = LiteEthUDPIPCore(self.etherbonephy, mac_address=etherbone_mac_address, ip_address=etherbone_ip_address, clk_freq=sys_clk_freq) self.submodules.etherbonecore = etherbonecore # Etherbone self.submodules.etherbone = LiteEthEtherbone( self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")
def __init__(self, platform, clk_freq, cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, integrated_rom_size=0, integrated_rom_init=[], integrated_sram_size=4096, integrated_sram_init=[], integrated_main_ram_size=0, integrated_main_ram_init=[], shadow_base=0x80000000, csr_data_width=8, csr_address_width=14, with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False, ident="", ident_version=False, wishbone_timeout_cycles=1e6, with_timer=True, with_ctrl=True): self.config = dict() self.platform = platform self.clk_freq = clk_freq self.soc_csr_map = {} self.soc_interrupt_map = {} self.soc_mem_map = self.mem_map # FIXME: RocketChip reserves the first 256Mbytes for internal use # remap rom to 0x10000000, sram to 0x20000000 if cpu_type == "rocket": self.soc_mem_map["rom"] = 0x10000000 self.soc_mem_map["sram"] = 0x20000000 if cpu_type == "None": cpu_type = None self.cpu_type = cpu_type # Support the old style which used underscore for separator if cpu_variant is None: cpu_variant = "standard" cpu_variant = cpu_variant.replace('_', '+') # Check for valid CPU variants. cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+') for key, values in CPU_VARIANTS.items(): if cpu_variant_processor not in [ key, ] + values: continue self.cpu_variant = key break else: raise InvalidCPUVariantError(cpu_variant) # Check for valid CPU extensions. for ext in sorted(cpu_variant_ext): if ext not in CPU_VARIANTS_EXTENSIONS: raise InvalidCPUExtensionError(cpu_variant) self.cpu_variant += "+" + ext if integrated_rom_size: cpu_reset_address = self.soc_mem_map["rom"] self.cpu_reset_address = cpu_reset_address self.config["CPU_RESET_ADDR"] = self.cpu_reset_address self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size self.with_uart = with_uart self.uart_baudrate = uart_baudrate self.shadow_base = shadow_base self.wishbone_timeout_cycles = wishbone_timeout_cycles self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width self.with_ctrl = with_ctrl self._memory_regions = [] # list of (name, origin, length) self._csr_regions = [ ] # list of (name, origin, busword, csr_list/Memory) self._constants = [] # list of (name, value) self._wb_masters = [] self._wb_slaves = [] self._csr_masters = [] # add user csrs for _name, _id in self.csr_map.items(): self.add_csr(_name, _id) if with_ctrl: self.submodules.ctrl = SoCController() self.add_csr("ctrl", allow_user_defined=True) if cpu_type is not None: if cpu_type == "lm32": self.add_cpu( lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "mor1kx" or cpu_type == "or1k": if cpu_type == "or1k": deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"") self.add_cpu( mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "picorv32": self.add_cpu( picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "vexriscv": self.add_cpu( vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "minerva": self.add_cpu( minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "rocket": self.add_cpu( rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant)) else: raise ValueError("Unsupported CPU type: {}".format(cpu_type)) self.add_csr("cpu", allow_user_defined=True) self.add_wb_master(self.cpu.ibus) self.add_wb_master(self.cpu.dbus) if with_ctrl: self.comb += self.cpu.reset.eq(self.ctrl.reset) # add cpu reserved interrupts for _name, _id in self.cpu.reserved_interrupts.items(): self.add_interrupt(_name, _id) # add user interrupts for _name, _id in self.interrupt_map.items(): self.add_interrupt(_name, _id) self.config["CPU_TYPE"] = str(cpu_type).upper() if self.cpu_variant: self.config["CPU_VARIANT"] = str(cpu_type).upper() if integrated_rom_size: self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init) self.register_rom(self.rom.bus, integrated_rom_size) if integrated_sram_size: self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init) self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size) # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping. if integrated_main_ram_size: self.submodules.main_ram = wishbone.SRAM( integrated_main_ram_size, init=integrated_main_ram_init) self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) self.submodules.wishbone2csr = wishbone2csr.WB2CSR( bus_csr=csr_bus.Interface(csr_data_width, csr_address_width)) self.add_csr_master(self.wishbone2csr.csr) self.config["CSR_DATA_WIDTH"] = csr_data_width self.add_constant("CSR_DATA_WIDTH", csr_data_width) self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone) if with_uart: if uart_stub: self.submodules.uart = uart.UARTStub() else: self.submodules.uart_phy = uart.RS232PHY( platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart = ResetInserter()(uart.UART( self.uart_phy)) self.add_csr("uart_phy", allow_user_defined=True) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) if ident: if ident_version: ident = ident + " " + version() self.submodules.identifier = identifier.Identifier(ident) self.add_csr("identifier_mem", allow_user_defined=True) self.config["CLOCK_FREQUENCY"] = int(clk_freq) self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq)) if with_timer: self.submodules.timer0 = timer.Timer() self.add_csr("timer0", allow_user_defined=True) self.add_interrupt("timer0", allow_user_defined=True)
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000001, etherbone_ip_address="192.168.1.51", with_analyzer=False, sdram_module="MT48LC16M16", sdram_init=[], sdram_data_width=32, sdram_verbosity=0, **kwargs): platform = Platform() sys_clk_freq = int(1e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteX Simulation", ident_version=True, l2_reverse=False, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART( self.uart_phy, tx_fifo_depth=kwargs["uart_fifo_depth"], rx_fifo_depth=kwargs["uart_fifo_depth"]) self.add_csr("uart") self.add_interrupt("uart") # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype, data_width=sdram_data_width, clk_freq=sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=sdram_verbosity, init=sdram_init) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # Reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8 * 1024) self.add_constant("MEMTEST_ADDR_SIZE", 8 * 1024) #assert not (with_ethernet and with_etherbone) if with_ethernet and with_etherbone: dw = 8 etherbone_ip_address = convert_ip(etherbone_ip_address) # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=dw, interface="hybrid", endianness=self.cpu.endianness, hw_mac=etherbone_mac_address) # SoftCPU self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # HW ethernet self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=dw) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=dw) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=dw) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=dw) # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Ethernet --------------------------------------------------------------------------------- elif with_ethernet: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # Ethernet MAC ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({ "eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx" })(ethmac) self.submodules.ethmac = ethmac self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # Etherbone -------------------------------------------------------------------------------- elif with_etherbone: # Ethernet PHY self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) # FIXME self.add_csr("ethphy") # Ethernet Core ethcore = LiteEthUDPIPCore(self.ethphy, mac_address=etherbone_mac_address, ip_address=etherbone_ip_address, clk_freq=sys_clk_freq) self.submodules.ethcore = ethcore # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [self.cpu.ibus, self.cpu.dbus] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")
def __init__(self, init_memories=False, with_sdram=False, sdram_module="MT48LC16M16", sdram_data_width=32, sdram_verbosity=0, with_ethernet=False): platform = Platform() sys_clk_freq = int(1e6) ram_init = [] if init_memories: ram_init = get_mem_data( { "buildroot/Image": "0x00000000", "buildroot/rootfs.cpio": "0x00800000", "buildroot/rv32.dtb": "0x01000000", }, "little") # SoCSDRAM ---------------------------------------------------------------------------------- SoCSDRAM.__init__( self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="linux", with_uart=False, l2_reverse=False, max_sdram_size=0x10000000, # Limit mapped SDRAM to 256MB for now integrated_rom_size=0x8000, integrated_main_ram_size=0x00000000 if with_sdram else 0x02000000, # 32MB integrated_main_ram_init=[] if (with_sdram or not init_memories) else ram_init) self.add_constant("SIM", None) # Supervisor ------------------------------------------------------------------------------- self.submodules.supervisor = Supervisor() self.add_csr("supervisor") # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) # Machine mode emulator RAM ---------------------------------------------------------------- emulator_rom = get_mem_data("emulator/emulator.bin", "little") if init_memories else [] self.submodules.emulator_ram = wishbone.SRAM(0x4000, init=emulator_rom) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["emulator_ram"]) # SDRAM ------------------------------------------------------------------------------------ if with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_rate = "1:{}".format( sdram_module_nphases[sdram_module_cls.memtype]) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) phy_settings = get_sdram_phy_settings(memtype=sdram_module.memtype, data_width=sdram_data_width, clk_freq=sdram_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(module=sdram_module, settings=phy_settings, clk_freq=sdram_clk_freq, verbosity=sdram_verbosity, init=ram_init) self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # FIXME: skip memtest to avoid corrupting memory self.add_constant("MEMTEST_BUS_SIZE", 0) self.add_constant("MEMTEST_ADDR_SIZE", 0) self.add_constant("MEMTEST_DATA_SIZE", 0) # Serial ----------------------------------------------------------------------------------- self.submodules.uart_phy = uart.RS232PHYModel( platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart", use_loc_if_exists=True) self.add_interrupt("uart", use_loc_if_exists=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel( self.platform.request("eth", 0)) self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.submodules.ethmac = ethmac self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, platform, clk_freq, cpu_type="lm32", cpu_reset_address=0x00000000, integrated_rom_size=0, integrated_sram_size=4096, integrated_main_ram_size=0, shadow_base=0x80000000, csr_data_width=8, csr_address_width=14, with_uart=True, uart_baudrate=115200, ident="", with_timer=True): self.platform = platform self.clk_freq = clk_freq self.cpu_type = cpu_type if integrated_rom_size: cpu_reset_address = 0 self.cpu_reset_address = cpu_reset_address self.integrated_rom_size = integrated_rom_size self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size self.with_uart = with_uart self.uart_baudrate = uart_baudrate self.shadow_base = shadow_base self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width self._memory_regions = [] # list of (name, origin, length) self._csr_regions = [ ] # list of (name, origin, busword, csr_list/Memory) self._constants = [] # list of (name, value) self._wb_masters = [] self._wb_slaves = [] if cpu_type is not None: if cpu_type == "lm32": self.add_cpu_or_bridge( lm32.LM32(platform, self.cpu_reset_address)) elif cpu_type == "or1k": self.add_cpu_or_bridge( mor1kx.MOR1KX(platform, self.cpu_reset_address)) elif cpu_type == "riscv32": self.add_cpu_or_bridge( picorv32.PicoRV32(platform, self.cpu_reset_address)) else: raise ValueError("Unsupported CPU type: {}".format(cpu_type)) self.add_wb_master(self.cpu_or_bridge.ibus) self.add_wb_master(self.cpu_or_bridge.dbus) if integrated_rom_size: self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True) self.register_rom(self.rom.bus, integrated_rom_size) if integrated_sram_size: self.submodules.sram = wishbone.SRAM(integrated_sram_size) self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size) # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping. if integrated_main_ram_size: self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size) self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) self.submodules.wishbone2csr = wishbone2csr.WB2CSR( bus_csr=csr_bus.Interface(csr_data_width, csr_address_width)) self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) if with_uart: self.submodules.uart_phy = uart.RS232PHY( platform.request("serial"), clk_freq, uart_baudrate) self.submodules.uart = uart.UART(self.uart_phy) if ident: self.submodules.identifier = identifier.Identifier(ident) self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq)) if with_timer: self.submodules.timer0 = timer.Timer()
def __init__(self, platform, clk_freq, cpu_type="lm32", cpu_reset_address=0x00000000, cpu_variant=None, integrated_rom_size=0, integrated_rom_init=[], integrated_sram_size=4096, integrated_main_ram_size=0, integrated_main_ram_init=[], shadow_base=0x80000000, csr_data_width=8, csr_address_width=14, with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False, ident="", ident_version=False, reserve_nmi_interrupt=True, with_timer=True): self.config = dict() self.platform = platform self.clk_freq = clk_freq self.cpu_type = cpu_type self.cpu_variant = cpu_variant if integrated_rom_size: cpu_reset_address = self.mem_map["rom"] self.cpu_reset_address = cpu_reset_address self.config["CPU_RESET_ADDR"] = self.cpu_reset_address self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size self.with_uart = with_uart self.uart_baudrate = uart_baudrate self.shadow_base = shadow_base self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width self._memory_regions = [] # list of (name, origin, length) self._csr_regions = [ ] # list of (name, origin, busword, csr_list/Memory) self._constants = [] # list of (name, value) self._wb_masters = [] self._wb_slaves = [] if cpu_type is not None: if cpu_type == "lm32": self.add_cpu_or_bridge( lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "or1k": self.add_cpu_or_bridge( mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "riscv32": self.add_cpu_or_bridge( picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant)) else: raise ValueError("Unsupported CPU type: {}".format(cpu_type)) self.add_wb_master(self.cpu_or_bridge.ibus) self.add_wb_master(self.cpu_or_bridge.dbus) self.config["CPU_TYPE"] = str(cpu_type).upper() if self.cpu_variant: self.config["CPU_VARIANT"] = str(cpu_type).upper() if integrated_rom_size: self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init) self.register_rom(self.rom.bus, integrated_rom_size) if integrated_sram_size: self.submodules.sram = wishbone.SRAM(integrated_sram_size) self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size) # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping. if integrated_main_ram_size: self.submodules.main_ram = wishbone.SRAM( integrated_main_ram_size, init=integrated_main_ram_init) self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) self.submodules.wishbone2csr = wishbone2csr.WB2CSR( bus_csr=csr_bus.Interface(csr_data_width, csr_address_width)) self.config["CSR_DATA_WIDTH"] = csr_data_width self.add_constant("CSR_DATA_WIDTH", csr_data_width) self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) if reserve_nmi_interrupt: self.soc_interrupt_map[ "nmi"] = 0 # Reserve zero for "non-maskable interrupt" if with_uart: if uart_stub: self.submodules.uart = uart.UARTStub() else: self.submodules.uart_phy = uart.RS232PHY( platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart = uart.UART(self.uart_phy) #else: # del self.soc_interrupt_map["uart"] if ident: if ident_version: ident = ident + " " + version() self.submodules.identifier = identifier.Identifier(ident) self.config["CLOCK_FREQUENCY"] = int(clk_freq) self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq)) if with_timer: self.submodules.timer0 = timer.Timer() else: del self.soc_interrupt_map["timer0"] # Invert the interrupt map. interrupt_rmap = {} for mod_name, interrupt in self.interrupt_map.items(): assert interrupt not in interrupt_rmap, ( "Interrupt vector conflict for IRQ %s, user defined %s conflicts with user defined %s" % (interrupt, mod_name, interrupt_rmap[interrupt])) interrupt_rmap[interrupt] = mod_name # Add the base SoC's interrupt map for mod_name, interrupt in self.soc_interrupt_map.items(): assert interrupt not in interrupt_rmap, ( "Interrupt vector conflict for IRQ %s, user defined %s conflicts with SoC inbuilt %s" % (interrupt, mod_name, interrupt_rmap[interrupt])) self.interrupt_map[mod_name] = interrupt interrupt_rmap[interrupt] = mod_name # Make sure other functions are not using this value. self.soc_interrupt_map = None # Make the interrupt vector read only self.interrupt_map = ReadOnlyDict(self.interrupt_map) # Save the interrupt reverse map self.interrupt_rmap = ReadOnlyDict(interrupt_rmap)
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e9/platform.default_clk_period) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # crg self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # serial self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # sdram if with_sdram: sdram_module = IS42S16160(sys_clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram( self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) # etherbone if with_etherbone: # eth phy self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME # eth core etherbonecore = LiteEthUDPIPCore(self.etherbonephy, etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq) if with_ethernet: etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore) self.submodules.etherbonecore = etherbonecore # etherbone self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # analyzer if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__( self, platform, clk_freq, # CPU parameters cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, # ROM parameters integrated_rom_size=0, integrated_rom_init=[], # SRAM parameters integrated_sram_size=4096, integrated_sram_init=[], # MAIN_RAM parameters integrated_main_ram_size=0, integrated_main_ram_init=[], # CSR parameters csr_data_width=8, csr_alignment=32, csr_address_width=14, # Identifier parameters ident="", ident_version=False, # UART parameters with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False, # Timer parameters with_timer=True, # Controller parameters with_ctrl=True, # Wishbone parameters with_wishbone=True, wishbone_timeout_cycles=1e6, **kwargs): self.platform = platform self.clk_freq = clk_freq # SoC's CSR/Mem/Interrupt mapping (default or user defined + dynamically allocateds) self.soc_csr_map = {} self.soc_interrupt_map = {} self.soc_mem_map = self.mem_map self.soc_io_regions = self.io_regions # SoC's Config/Constants/Regions self.config = {} self.constants = {} self.mem_regions = {} self.csr_regions = {} # Wishbone masters/slaves lists self._wb_masters = [] self._wb_slaves = [] # CSR masters list self._csr_masters = [] self.add_retro_compat(kwargs) # Parameters managment --------------------------------------------------------------------- if cpu_type == "None": cpu_type = None if not with_wishbone: self.soc_mem_map["csr"] = 0x00000000 self.cpu_type = cpu_type self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant) self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size assert csr_data_width in [8, 32, 64] assert 2**(csr_address_width + 2) <= 0x1000000 self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width self.with_ctrl = with_ctrl self.with_uart = with_uart self.uart_baudrate = uart_baudrate self.with_wishbone = with_wishbone self.wishbone_timeout_cycles = wishbone_timeout_cycles # Modules instances ------------------------------------------------------------------------ # Add user's CSRs (needs to be done before the first dynamic allocation) for _name, _id in self.csr_map.items(): self.add_csr(_name, _id) # Add SoCController if with_ctrl: self.submodules.ctrl = SoCController() self.add_csr("ctrl", allow_user_defined=True) # Add CPU self.config["CPU_TYPE"] = str(cpu_type).upper() if cpu_type is not None: if cpu_variant is not None: self.config["CPU_VARIANT"] = str( cpu_variant.split('+')[0]).upper() # Check type if cpu_type not in cpu.CPUS.keys(): raise ValueError("Unsupported CPU type: {}".format(cpu_type)) # Add the CPU self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_variant)) # Update Memory Map (if defined by CPU) self.soc_mem_map.update(self.cpu.mem_map) # Update IO Regions (if defined by CPU) self.soc_io_regions.update(self.cpu.io_regions) # Set reset address self.cpu.set_reset_address( self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address) self.config["CPU_RESET_ADDR"] = self.cpu.reset_address # Add CPU buses as 32-bit Wishbone masters for cpu_bus in self.cpu.buses: assert cpu_bus.data_width in [32, 64, 128] soc_bus = wishbone.Interface(data_width=32) self.submodules += wishbone.Converter(cpu_bus, soc_bus) self.add_wb_master(soc_bus) # Add CPU CSR (dynamic) self.add_csr("cpu", allow_user_defined=True) # Add CPU interrupts for _name, _id in self.cpu.interrupts.items(): self.add_interrupt(_name, _id) # Allow SoCController to reset the CPU if with_ctrl: self.comb += self.cpu.reset.eq(self.ctrl.reset) else: self.add_cpu(cpu.CPUNone()) self.soc_io_regions.update(self.cpu.io_regions) # Add user's interrupts (needs to be done after CPU interrupts are allocated) for _name, _id in self.interrupt_map.items(): self.add_interrupt(_name, _id) # Add integrated ROM if integrated_rom_size: self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init) self.register_rom(self.rom.bus, integrated_rom_size) # Add integrated SRAM if integrated_sram_size: self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init) self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size) # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available) if integrated_main_ram_size: self.submodules.main_ram = wishbone.SRAM( integrated_main_ram_size, init=integrated_main_ram_init) self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) # Add UART if with_uart: if uart_stub: self.submodules.uart = uart.UARTStub() else: if uart_name == "jtag_atlantic": from litex.soc.cores.jtag import JTAGAtlantic self.submodules.uart_phy = JTAGAtlantic() elif uart_name == "jtag_uart": from litex.soc.cores.jtag import JTAGPHY self.submodules.uart_phy = JTAGPHY(device=platform.device) else: self.submodules.uart_phy = uart.UARTPHY( platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart = ResetInserter()(uart.UART( self.uart_phy)) self.add_csr("uart_phy", allow_user_defined=True) self.add_csr("uart", allow_user_defined=True) self.add_interrupt("uart", allow_user_defined=True) # Add Identifier if ident: if ident_version: ident = ident + " " + get_version() self.submodules.identifier = identifier.Identifier(ident) self.add_csr("identifier_mem", allow_user_defined=True) self.config["CLOCK_FREQUENCY"] = int(clk_freq) # Add Timer if with_timer: self.submodules.timer0 = timer.Timer() self.add_csr("timer0", allow_user_defined=True) self.add_interrupt("timer0", allow_user_defined=True) # Add Wishbone to CSR bridge csr_alignment = max(csr_alignment, self.cpu.data_width) self.config["CSR_DATA_WIDTH"] = csr_data_width self.config["CSR_ALIGNMENT"] = csr_alignment self.csr_data_width = csr_data_width self.csr_alignment = csr_alignment if with_wishbone: self.submodules.wishbone2csr = wishbone2csr.WB2CSR( bus_csr=csr_bus.Interface(address_width=csr_address_width, data_width=csr_data_width)) self.add_csr_master(self.wishbone2csr.csr) self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)
def __init__(self, simulate, sdram_init=[], with_analyzer=False): self.simulate = simulate if simulate: platform = litex_platform_n64.N64SimPlatform() else: platform = litex_platform_n64.Platform() sys_clk_freq = int(48e6) kwargs = {} kwargs["clk_freq"] = sys_clk_freq kwargs["cpu_type"] = "vexriscv" kwargs["cpu_variant"] = "minimal" kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 2*kB kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset if simulate: kwargs["with_uart"] = False kwargs["with_ethernet"] = False # SoCMini ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, **kwargs) if simulate: self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) self.add_csr("uart") self.add_interrupt("uart") if not self.integrated_main_ram_size: if simulate: sdram_data_width = 16 sdram_module = IS42S16320(sys_clk_freq, "1:1") phy_settings = get_sdram_phy_settings( memtype = sdram_module.memtype, data_width = sdram_data_width, clk_freq = sys_clk_freq) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings, init=sdram_init) self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) else: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, module = IS42S16320(sys_clk_freq, "1:1"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x4000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # CRG -------------------------------------------------------------------------------------- if simulate: self.submodules.crg = CRG(platform.request("sys_clk")) else: self.submodules.crg = _CRG(platform, sys_clk_freq) if simulate: integrated_rom_init = get_mem_data("build/software/bios/bios.bin", "little") self.add_rom("rom", self.cpu.reset_address, len(integrated_rom_init)*4, integrated_rom_init) else: self.submodules.spiflash = SpiFlash(platform.request("spiflash"), dummy=8, endianness="little") self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=8*mB) self.add_csr("spiflash") self.add_memory_region("rom", self.mem_map["spiflash"] + bios_flash_offset, 32*kB, type="cached+linker") # Led -------------------------------------------------------------------------------------- self.submodules.led = GPIOOut(platform.request("io0")) self.add_csr("led") # GPIOs ------------------------------------------------------------------------------------ self.submodules.gpio0 = GPIOOut(platform.request("io1")) self.add_csr("gpio0") self.submodules.gpio1 = GPIOOut(platform.request("io2")) self.add_csr("gpio1") platform.add_extension(_gpios) if with_analyzer: analyzer_signals = [ self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) self.add_csr("analyzer")