def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = zybo_z7.Platform()
if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB.
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Zybo Z7",
ident_version = True,
**kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
os.system("wget https://github.com/litex-hub/litex-boards/files/4967144/zybo_z7_ps7.txt")
os.makedirs("xci", exist_ok=True)
os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi = self.cpu.add_axi_gp_master(),
wishbone = wb_gp0,
base_address = 0x43c00000)
self.add_wb_master(wb_gp0)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = ebaz4205_z7.Platform()
if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "data1_uart" # Use DATA1 connector for UART
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on EBAZ4205",
ident_version = True,
**kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
os.makedirs("xci", exist_ok=True)
os.system("cp ebaz4205_z7_ps7.xci xci/ebaz4205_z7_ps7.xci")
self.cpu.set_ps7_xci("xci/ebaz4205_z7_ps7.xci")
# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi = self.cpu.add_axi_gp_master(),
wishbone = wb_gp0,
base_address = 0x43c00000)
self.add_wb_master(wb_gp0)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
with_led_chaser=True,
with_video_terminal=False,
with_video_framebuffer=False,
**kwargs):
platform = pynq_z1.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on PYNQ Z1",
**kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
os.system(
"wget https://github.com/litex-hub/litex-boards/files/4967144/zybo_z7_ps7.txt"
)
os.makedirs("xci", exist_ok=True)
os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi=self.cpu.add_axi_gp_master(),
wishbone=wb_gp0,
base_address=0x43c00000)
self.add_wb_master(wb_gp0)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
toolchain,
with_video_pll=with_video_terminal)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoS7HDMIPHY(
platform.request("hdmi_tx"), clock_domain="hdmi")
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(25e6), with_led_chaser=True, **kwargs):
platform = alinx_axu2cga.Platform()
if kwargs.get("cpu_type", None) == "zynqmp":
kwargs['integrated_sram_size'] = 0
kwargs['with_uart'] = False
self.mem_map = {
'csr': 0x8000_0000, # Zynq GP0 default
}
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Alinx AXU2CGA",
**kwargs)
# ZynqMP Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynqmp":
self.cpu.config.update(platform.psu_config)
# Connect AXI HPM0 LPD to the SoC
wb_lpd = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi=self.cpu.add_axi_gp_master(2, 32),
wishbone=wb_lpd,
base_address=self.mem_map['csr'])
self.add_wb_master(wb_lpd)
self.bus.add_region(
"sram",
SoCRegion(origin=self.cpu.mem_map["sram"],
size=1 * 1024 * 1024 * 1024) # DDR
)
self.bus.add_region(
"rom",
SoCRegion(origin=self.cpu.mem_map["rom"],
size=512 * 1024 * 1024 // 8,
linker=True))
self.constants['CONFIG_CLOCK_FREQUENCY'] = 1199880127
use_psu_clk = True
else:
use_psu_clk = False
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_psu_clk)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
variant="z7-20",
toolchain="vivado",
sys_clk_freq=int(125e6),
with_led_chaser=True,
**kwargs):
platform = digilent_arty_z7.Platform(variant=variant,
toolchain=toolchain)
if kwargs.get("cpu_type", None) == "zynq7000":
kwargs['integrated_sram_size'] = 0
kwargs['with_uart'] = False
self.mem_map = {
'csr': 0x4000_0000, # Zynq GP0 default
}
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty Z7",
**kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
assert toolchain == "vivado", ' not tested / specific vivado cmds'
preset_name = "arty_z7_20.tcl" if variant == "z7-20" else "arty_z7_10.tcl"
os.system("wget http://kmf2.trabucayre.com/" + preset_name)
self.cpu.set_ps7(preset=preset_name)
# Connect AXI GP0 to the SoC
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi=self.cpu.add_axi_gp_master(),
wishbone=wb_gp0,
base_address=self.mem_map['csr'])
self.add_wb_master(wb_gp0)
use_ps7_clk = True
else:
use_ps7_clk = False
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq, with_led_chaser=True, **kwargs):
platform = digilent_zedboard.Platform()
if kwargs.get("cpu_type", None) == "zynq7000":
kwargs['integrated_sram_size'] = 0
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Zedboard",
**kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
self.cpu.set_ps7(
name="Zynq",
preset="ZedBoard",
config={'PCW_FPGA0_PERIPHERAL_FREQMHZ': sys_clk_freq / 1e6})
# Connect AXI GP0 to the SoC
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi=self.cpu.add_axi_gp_master(),
wishbone=wb_gp0,
base_address=self.mem_map["csr"])
self.add_wb_master(wb_gp0)
self.bus.add_region(
"sram",
SoCRegion(origin=self.cpu.mem_map["sram"],
size=512 * 1024 * 1024 - self.cpu.mem_map["sram"]))
self.bus.add_region(
"rom",
SoCRegion(origin=self.cpu.mem_map["rom"],
size=256 * 1024 * 1024 // 8,
linker=True))
self.constants['CONFIG_CLOCK_FREQUENCY'] = 666666687
use_ps7_clk = True
else:
use_ps7_clk = False
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
variant="z7-10",
sys_clk_freq=int(100e6),
with_led_chaser=True,
ext_clk_freq=None,
xci_file=None,
**kwargs):
platform = snickerdoodle.Platform(variant=variant)
if ext_clk_freq:
platform.default_clk_freq = ext_clk_freq
platform.default_clk_period = 1e9 / ext_clk_freq
if kwargs.get("cpu_type", None) == "zynq7000":
kwargs["integrated_sram_size"] = 0
kwargs["with_uart"] = False
self.mem_map = {"csr": 0x4000_0000} # Zynq GP0 default
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Snickerdoodle",
**kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
load_ps7(self, xci_file)
# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi=self.cpu.add_axi_gp_master(),
wishbone=wb_gp0,
base_address=self.mem_map['csr'])
self.add_wb_master(wb_gp0)
use_ps7_clk = True
else:
use_ps7_clk = False
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
board,
sys_clk_freq=int(100e6),
with_led_chaser=True,
**kwargs):
platform = redpitaya.Platform(board)
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "usb_uart"
use_ps7_clk = False
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Zebboard",
ident_version=True,
**kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
os.system("wget https://kmf2.trabucayre.com/redpitaya_ps7.txt")
os.makedirs("xci", exist_ok=True)
os.system("cp redpitaya_ps7.txt xci/redpitaya_ps7.xci")
self.cpu.set_ps7_xci("xci/redpitaya_ps7.xci")
# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi=self.cpu.add_axi_gp_master(),
wishbone=wb_gp0,
base_address=0x43c00000)
self.add_wb_master(wb_gp0)
use_ps7_clk = True
sys_clk_freq = 125e6
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = zedboard.Platform()
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "usb_acm" # Use USB-UART Pmod on JB.
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Zedboard",
ident_version=True,
**kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
# Connect AXI GP0 to the SoC. See UG585 p. 112 for base_address
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi=self.cpu.add_axi_gp_master(),
wishbone=wb_gp0,
base_address=0x40000000)
self.add_wb_master(wb_gp0)
# CRG --------------------------------------------------------------------------------------
# self.submodules.crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = _CRG(platform, sys_clk_freq, True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# OLED display -----------------------------------------------------------------------------
self.cpu.add_emio_gpio()
self.add_oled()
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(8)
mem_dw, mmio_dw, num_cores = CPU_SIZE_PARAMS[self.variant]
self.mem_axi = mem_axi = axi.AXIInterface(data_width=mem_dw,
address_width=32,
id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw,
address_width=32,
id_width=4)
self.l2fb_axi = l2fb_axi = axi.AXIInterface(data_width=mmio_dw,
address_width=32,
id_width=4)
self.mmio_wb = mmio_wb = wishbone.Interface(data_width=mmio_dw,
adr_width=32 -
log2_int(mmio_dw // 8))
self.l2fb_wb = l2fb_wb = wishbone.Interface(data_width=mmio_dw,
adr_width=32 -
log2_int(mmio_dw // 8))
self.memory_buses = [
mem_axi
] # Peripheral buses (Connected to main SoC's bus).
self.periph_buses = [
mmio_wb
] # Memory buses (Connected directly to LiteDRAM).
self.dma_bus = l2fb_wb # DMA bus (Arbitrated and connected to SoC's bus).
# # #
self.cpu_params = dict(
# Clk / Rst.
i_clock=ClockSignal("sys"),
i_reset=ResetSignal("sys") | self.reset,
# Debug (ignored).
i_debug_clock=0,
i_debug_reset=ResetSignal() | self.reset,
o_debug_clockeddmi_dmi_req_ready=Open(),
i_debug_clockeddmi_dmi_req_valid=0,
i_debug_clockeddmi_dmi_req_bits_addr=0,
i_debug_clockeddmi_dmi_req_bits_data=0,
i_debug_clockeddmi_dmi_req_bits_op=0,
i_debug_clockeddmi_dmi_resp_ready=0,
o_debug_clockeddmi_dmi_resp_valid=Open(),
o_debug_clockeddmi_dmi_resp_bits_data=Open(),
o_debug_clockeddmi_dmi_resp_bits_resp=Open(),
i_debug_clockeddmi_dmiClock=0,
i_debug_clockeddmi_dmiReset=ResetSignal() | self.reset,
o_debug_ndreset=Open(),
o_debug_dmactive=Open(),
i_debug_dmactiveAck=0,
# IRQ.
i_interrupts=self.interrupt,
# AXI Memory (L1-cached).
i_mem_axi4_0_aw_ready=mem_axi.aw.ready,
o_mem_axi4_0_aw_valid=mem_axi.aw.valid,
o_mem_axi4_0_aw_bits_id=mem_axi.aw.id,
o_mem_axi4_0_aw_bits_addr=mem_axi.aw.addr,
o_mem_axi4_0_aw_bits_len=mem_axi.aw.len,
o_mem_axi4_0_aw_bits_size=mem_axi.aw.size,
o_mem_axi4_0_aw_bits_burst=mem_axi.aw.burst,
o_mem_axi4_0_aw_bits_lock=mem_axi.aw.lock,
o_mem_axi4_0_aw_bits_cache=mem_axi.aw.cache,
o_mem_axi4_0_aw_bits_prot=mem_axi.aw.prot,
o_mem_axi4_0_aw_bits_qos=mem_axi.aw.qos,
i_mem_axi4_0_w_ready=mem_axi.w.ready,
o_mem_axi4_0_w_valid=mem_axi.w.valid,
o_mem_axi4_0_w_bits_data=mem_axi.w.data,
o_mem_axi4_0_w_bits_strb=mem_axi.w.strb,
o_mem_axi4_0_w_bits_last=mem_axi.w.last,
o_mem_axi4_0_b_ready=mem_axi.b.ready,
i_mem_axi4_0_b_valid=mem_axi.b.valid,
i_mem_axi4_0_b_bits_id=mem_axi.b.id,
i_mem_axi4_0_b_bits_resp=mem_axi.b.resp,
i_mem_axi4_0_ar_ready=mem_axi.ar.ready,
o_mem_axi4_0_ar_valid=mem_axi.ar.valid,
o_mem_axi4_0_ar_bits_id=mem_axi.ar.id,
o_mem_axi4_0_ar_bits_addr=mem_axi.ar.addr,
o_mem_axi4_0_ar_bits_len=mem_axi.ar.len,
o_mem_axi4_0_ar_bits_size=mem_axi.ar.size,
o_mem_axi4_0_ar_bits_burst=mem_axi.ar.burst,
o_mem_axi4_0_ar_bits_lock=mem_axi.ar.lock,
o_mem_axi4_0_ar_bits_cache=mem_axi.ar.cache,
o_mem_axi4_0_ar_bits_prot=mem_axi.ar.prot,
o_mem_axi4_0_ar_bits_qos=mem_axi.ar.qos,
o_mem_axi4_0_r_ready=mem_axi.r.ready,
i_mem_axi4_0_r_valid=mem_axi.r.valid,
i_mem_axi4_0_r_bits_id=mem_axi.r.id,
i_mem_axi4_0_r_bits_data=mem_axi.r.data,
i_mem_axi4_0_r_bits_resp=mem_axi.r.resp,
i_mem_axi4_0_r_bits_last=mem_axi.r.last,
# AXI MMIO (not cached).
i_mmio_axi4_0_aw_ready=mmio_axi.aw.ready,
o_mmio_axi4_0_aw_valid=mmio_axi.aw.valid,
o_mmio_axi4_0_aw_bits_id=mmio_axi.aw.id,
o_mmio_axi4_0_aw_bits_addr=mmio_axi.aw.addr,
o_mmio_axi4_0_aw_bits_len=mmio_axi.aw.len,
o_mmio_axi4_0_aw_bits_size=mmio_axi.aw.size,
o_mmio_axi4_0_aw_bits_burst=mmio_axi.aw.burst,
o_mmio_axi4_0_aw_bits_lock=mmio_axi.aw.lock,
o_mmio_axi4_0_aw_bits_cache=mmio_axi.aw.cache,
o_mmio_axi4_0_aw_bits_prot=mmio_axi.aw.prot,
o_mmio_axi4_0_aw_bits_qos=mmio_axi.aw.qos,
i_mmio_axi4_0_w_ready=mmio_axi.w.ready,
o_mmio_axi4_0_w_valid=mmio_axi.w.valid,
o_mmio_axi4_0_w_bits_data=mmio_axi.w.data,
o_mmio_axi4_0_w_bits_strb=mmio_axi.w.strb,
o_mmio_axi4_0_w_bits_last=mmio_axi.w.last,
o_mmio_axi4_0_b_ready=mmio_axi.b.ready,
i_mmio_axi4_0_b_valid=mmio_axi.b.valid,
i_mmio_axi4_0_b_bits_id=mmio_axi.b.id,
i_mmio_axi4_0_b_bits_resp=mmio_axi.b.resp,
i_mmio_axi4_0_ar_ready=mmio_axi.ar.ready,
o_mmio_axi4_0_ar_valid=mmio_axi.ar.valid,
o_mmio_axi4_0_ar_bits_id=mmio_axi.ar.id,
o_mmio_axi4_0_ar_bits_addr=mmio_axi.ar.addr,
o_mmio_axi4_0_ar_bits_len=mmio_axi.ar.len,
o_mmio_axi4_0_ar_bits_size=mmio_axi.ar.size,
o_mmio_axi4_0_ar_bits_burst=mmio_axi.ar.burst,
o_mmio_axi4_0_ar_bits_lock=mmio_axi.ar.lock,
o_mmio_axi4_0_ar_bits_cache=mmio_axi.ar.cache,
o_mmio_axi4_0_ar_bits_prot=mmio_axi.ar.prot,
o_mmio_axi4_0_ar_bits_qos=mmio_axi.ar.qos,
o_mmio_axi4_0_r_ready=mmio_axi.r.ready,
i_mmio_axi4_0_r_valid=mmio_axi.r.valid,
i_mmio_axi4_0_r_bits_id=mmio_axi.r.id,
i_mmio_axi4_0_r_bits_data=mmio_axi.r.data,
i_mmio_axi4_0_r_bits_resp=mmio_axi.r.resp,
i_mmio_axi4_0_r_bits_last=mmio_axi.r.last,
# AXI L2FB (Slave, for e.g., DMA).
o_l2_frontend_bus_axi4_0_aw_ready=l2fb_axi.aw.ready,
i_l2_frontend_bus_axi4_0_aw_valid=l2fb_axi.aw.valid,
i_l2_frontend_bus_axi4_0_aw_bits_id=l2fb_axi.aw.id,
i_l2_frontend_bus_axi4_0_aw_bits_addr=l2fb_axi.aw.addr,
i_l2_frontend_bus_axi4_0_aw_bits_len=l2fb_axi.aw.len,
i_l2_frontend_bus_axi4_0_aw_bits_size=l2fb_axi.aw.size,
i_l2_frontend_bus_axi4_0_aw_bits_burst=l2fb_axi.aw.burst,
i_l2_frontend_bus_axi4_0_aw_bits_lock=l2fb_axi.aw.lock,
i_l2_frontend_bus_axi4_0_aw_bits_cache=l2fb_axi.aw.cache,
i_l2_frontend_bus_axi4_0_aw_bits_prot=l2fb_axi.aw.prot,
i_l2_frontend_bus_axi4_0_aw_bits_qos=l2fb_axi.aw.qos,
o_l2_frontend_bus_axi4_0_w_ready=l2fb_axi.w.ready,
i_l2_frontend_bus_axi4_0_w_valid=l2fb_axi.w.valid,
i_l2_frontend_bus_axi4_0_w_bits_data=l2fb_axi.w.data,
i_l2_frontend_bus_axi4_0_w_bits_strb=l2fb_axi.w.strb,
i_l2_frontend_bus_axi4_0_w_bits_last=l2fb_axi.w.last,
i_l2_frontend_bus_axi4_0_b_ready=l2fb_axi.b.ready,
o_l2_frontend_bus_axi4_0_b_valid=l2fb_axi.b.valid,
o_l2_frontend_bus_axi4_0_b_bits_id=l2fb_axi.b.id,
o_l2_frontend_bus_axi4_0_b_bits_resp=l2fb_axi.b.resp,
o_l2_frontend_bus_axi4_0_ar_ready=l2fb_axi.ar.ready,
i_l2_frontend_bus_axi4_0_ar_valid=l2fb_axi.ar.valid,
i_l2_frontend_bus_axi4_0_ar_bits_id=l2fb_axi.ar.id,
i_l2_frontend_bus_axi4_0_ar_bits_addr=l2fb_axi.ar.addr,
i_l2_frontend_bus_axi4_0_ar_bits_len=l2fb_axi.ar.len,
i_l2_frontend_bus_axi4_0_ar_bits_size=l2fb_axi.ar.size,
i_l2_frontend_bus_axi4_0_ar_bits_burst=l2fb_axi.ar.burst,
i_l2_frontend_bus_axi4_0_ar_bits_lock=l2fb_axi.ar.lock,
i_l2_frontend_bus_axi4_0_ar_bits_cache=l2fb_axi.ar.cache,
i_l2_frontend_bus_axi4_0_ar_bits_prot=l2fb_axi.ar.prot,
i_l2_frontend_bus_axi4_0_ar_bits_qos=l2fb_axi.ar.qos,
i_l2_frontend_bus_axi4_0_r_ready=l2fb_axi.r.ready,
o_l2_frontend_bus_axi4_0_r_valid=l2fb_axi.r.valid,
o_l2_frontend_bus_axi4_0_r_bits_id=l2fb_axi.r.id,
o_l2_frontend_bus_axi4_0_r_bits_data=l2fb_axi.r.data,
o_l2_frontend_bus_axi4_0_r_bits_resp=l2fb_axi.r.resp,
o_l2_frontend_bus_axi4_0_r_bits_last=l2fb_axi.r.last,
)
# additional per-core debug signals:
self.cpu_params.update({
'i_resetctrl_hartIsInReset_%s' % i: Open()
for i in range(num_cores)
})
# Adapt AXI interfaces to Wishbone.
mmio_a2w = axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0)
self.submodules += mmio_a2w
l2fb_a2w = axi.Wishbone2AXI(l2fb_wb, l2fb_axi, base_address=0)
self.submodules += l2fb_a2w
# Add Verilog sources.
self.add_sources(platform, variant)
def __init__(self, sys_clk_freq, with_led_chaser=True, **kwargs):
platform = xilinx_zcu216.Platform()
if kwargs.get("cpu_type", None) == "zynqmp":
kwargs['integrated_sram_size'] = 0
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ZCU216",
**kwargs)
# ZynqMP Integration -----------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynqmp":
# generated from board xml presets
self.cpu.config.update({
'PSU__CRF_APB__ACPU_CTRL__FREQMHZ': '1200',
'PSU__DDRC__BANK_ADDR_COUNT': '2',
'PSU__DDRC__BG_ADDR_COUNT': '1',
'PSU__DDRC__BRC_MAPPING': 'ROW_BANK_COL',
'PSU__DDRC__BUS_WIDTH': '64 Bit',
'PSU__DDRC__CL': '15',
'PSU__DDRC__CLOCK_STOP_EN': '0',
'PSU__DDRC__COL_ADDR_COUNT': '10',
'PSU__DDRC__COMPONENTS': 'UDIMM',
'PSU__DDRC__CWL': '11',
'PSU__DDRC__DDR4_ADDR_MAPPING': '0',
'PSU__DDRC__DDR4_CAL_MODE_ENABLE': '0',
'PSU__DDRC__DDR4_CRC_CONTROL': '0',
'PSU__DDRC__DDR4_T_REF_MODE': '0',
'PSU__DDRC__DDR4_T_REF_RANGE': 'Normal (0-85)',
'PSU__DDRC__DEVICE_CAPACITY': '8192 MBits',
'PSU__DDRC__DIMM_ADDR_MIRROR': '0',
'PSU__DDRC__DM_DBI': 'DM_NO_DBI',
'PSU__DDRC__DRAM_WIDTH': '16 Bits',
'PSU__DDRC__ECC': 'Disabled',
'PSU__DDRC__FGRM': '1X',
'PSU__DDRC__LP_ASR': 'manual normal',
'PSU__DDRC__MEMORY_TYPE': 'DDR 4',
'PSU__DDRC__PARITY_ENABLE': '0',
'PSU__DDRC__PER_BANK_REFRESH': '0',
'PSU__DDRC__PHY_DBI_MODE': '0',
'PSU__DDRC__RANK_ADDR_COUNT': '0',
'PSU__DDRC__ROW_ADDR_COUNT': '16',
'PSU__DDRC__SELF_REF_ABORT': '0',
'PSU__DDRC__SPEED_BIN': 'DDR4_2133P',
'PSU__DDRC__STATIC_RD_MODE': '0',
'PSU__DDRC__TRAIN_DATA_EYE': '1',
'PSU__DDRC__TRAIN_READ_GATE': '1',
'PSU__DDRC__TRAIN_WRITE_LEVEL': '1',
'PSU__DDRC__T_FAW': '30.0',
'PSU__DDRC__T_RAS_MIN': '33',
'PSU__DDRC__T_RC': '46.5',
'PSU__DDRC__T_RCD': '15',
'PSU__DDRC__T_RP': '15',
'PSU__DDRC__VREF': '1',
'PSU__UART0__PERIPHERAL__ENABLE': '1',
'PSU__UART0__PERIPHERAL__IO': 'MIO 18 .. 19',
})
# Connect Zynq AXI master to the SoC
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi = self.cpu.add_axi_gp_master(),
wishbone = wb_gp0,
base_address = self.mem_map["csr"])
self.add_wb_master(wb_gp0)
self.bus.add_region("sram", SoCRegion(
origin=self.cpu.mem_map["sram"],
size=2 * 1024 * 1024 * 1024) # DDR
)
self.bus.add_region("rom", SoCRegion(
origin=self.cpu.mem_map["rom"],
size=512 * 1024 * 1024 // 8,
linker=True)
)
self.constants['CONFIG_CLOCK_FREQUENCY'] = 1200000000
use_ps7_clk = True
else:
use_ps7_clk = False
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
# LEDs -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq, **kwargs):
platform = xilinx_kv260.Platform()
if kwargs.get("cpu_type", None) == "zynqmp":
kwargs['integrated_sram_size'] = 0
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KV260",
**kwargs)
# ZynqMP Integration -----------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynqmp":
self.cpu.config.update({
'PSU_MIO_36_DIRECTION':
'out',
'PSU_MIO_37_DIRECTION':
'in',
'PSU__UART1__BAUD_RATE':
115200,
'PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0':
10,
})
# generated from board xml presets
self.cpu.config.update({
'PSU__CRF_APB__ACPU_CTRL__FREQMHZ':
'1333.333',
'PSU__DDRC__BANK_ADDR_COUNT':
'2',
'PSU__DDRC__BG_ADDR_COUNT':
'1',
'PSU__DDRC__BRC_MAPPING':
'ROW_BANK_COL',
'PSU__DDRC__BUS_WIDTH':
'64 Bit',
'PSU__DDRC__CL':
'16',
'PSU__DDRC__CLOCK_STOP_EN':
'0',
'PSU__DDRC__COL_ADDR_COUNT':
'10',
'PSU__DDRC__COMPONENTS':
'Components',
'PSU__DDRC__CWL':
'12',
'PSU__DDRC__DDR4_ADDR_MAPPING':
'0',
'PSU__DDRC__DDR4_CAL_MODE_ENABLE':
'0',
'PSU__DDRC__DDR4_CRC_CONTROL':
'0',
'PSU__DDRC__DDR4_T_REF_MODE':
'0',
'PSU__DDRC__DDR4_T_REF_RANGE':
'Normal (0-85)',
'PSU__DDRC__DEVICE_CAPACITY':
'8192 MBits',
'PSU__DDRC__DIMM_ADDR_MIRROR':
'0',
'PSU__DDRC__DM_DBI':
'DM_NO_DBI',
'PSU__DDRC__DRAM_WIDTH':
'16 Bits',
'PSU__DDRC__ECC':
'Disabled',
'PSU__DDRC__FGRM':
'1X',
'PSU__DDRC__LP_ASR':
'manual normal',
'PSU__DDRC__MEMORY_TYPE':
'DDR 4',
'PSU__DDRC__PARITY_ENABLE':
'0',
'PSU__DDRC__PER_BANK_REFRESH':
'0',
'PSU__DDRC__PHY_DBI_MODE':
'0',
'PSU__DDRC__RANK_ADDR_COUNT':
'0',
'PSU__DDRC__ROW_ADDR_COUNT':
'16',
'PSU__DDRC__SELF_REF_ABORT':
'0',
'PSU__DDRC__SPEED_BIN':
'DDR4_2400R',
'PSU__DDRC__STATIC_RD_MODE':
'0',
'PSU__DDRC__TRAIN_DATA_EYE':
'1',
'PSU__DDRC__TRAIN_READ_GATE':
'1',
'PSU__DDRC__TRAIN_WRITE_LEVEL':
'1',
'PSU__DDRC__T_FAW':
'30.0',
'PSU__DDRC__T_RAS_MIN':
'33',
'PSU__DDRC__T_RC':
'47.06',
'PSU__DDRC__T_RCD':
'16',
'PSU__DDRC__T_RP':
'16',
'PSU__DDRC__VREF':
'1',
'PSU__FPGA_PL0_ENABLE':
'1',
'PSU__PMU__GPO4__ENABLE':
'0', # these 2 are disabled for uart1
'PSU__PMU__GPO5__ENABLE':
'0',
'PSU__UART1__PERIPHERAL__ENABLE':
'1',
'PSU__UART1__PERIPHERAL__IO':
'MIO 36 .. 37',
})
# Connect Zynq AXI master to the SoC
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi=self.cpu.add_axi_gp_master(),
wishbone=wb_gp0,
base_address=self.mem_map["csr"])
self.add_wb_master(wb_gp0)
self.bus.add_region(
"sram",
SoCRegion(origin=self.cpu.mem_map["sram"],
size=2 * 1024 * 1024 * 1024) # DDR
)
self.bus.add_region(
"rom",
SoCRegion(origin=self.cpu.mem_map["rom"],
size=512 * 1024 * 1024 // 8,
linker=True))
self.constants['CONFIG_CLOCK_FREQUENCY'] = 1333333008
use_ps7_clk = True
else:
use_ps7_clk = False
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
def add_sdram(self, name, phy, module, origin, size=None,
l2_cache_size = 8192,
l2_cache_min_data_width = 128,
l2_cache_reverse = True,
l2_cache_full_memory_we = True,
**kwargs):
# LiteDRAM core ----------------------------------------------------------------------------
self.submodules.sdram = LiteDRAMCore(
phy = phy,
geom_settings = module.geom_settings,
timing_settings = module.timing_settings,
clk_freq = self.sys_clk_freq,
**kwargs)
self.csr.add("sdram")
# LiteDRAM port ----------------------------------------------------------------------------
port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
# SDRAM size -------------------------------------------------------------------------------
sdram_size = 2**(module.geom_settings.bankbits +
module.geom_settings.rowbits +
module.geom_settings.colbits)*phy.settings.databits//8
if size is not None:
sdram_size = min(sdram_size, size)
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
# SoC [<--> L2 Cache] <--> LiteDRAM --------------------------------------------------------
if self.cpu.name == "rocket":
# Rocket has its own I/D L1 cache: connect directly to LiteDRAM when possible.
if port.data_width == self.cpu.mem_axi.data_width:
self.logger.info("Matching AXI MEM data width ({})\n".format(port.data_width))
self.submodules += LiteDRAMAXI2Native(
axi = self.cpu.mem_axi,
port = port,
base_address = self.bus.regions["main_ram"].origin)
else:
self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
port.data_width,
self.cpu.mem_axi.data_width))
# FIXME: replace WB data-width converter with native AXI converter!!!
mem_wb = wishbone.Interface(
data_width = self.cpu.mem_axi.data_width,
adr_width = 32-log2_int(self.cpu.mem_axi.data_width//8))
# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
mem_a2w = ResetInserter()(axi.AXI2Wishbone(
axi = self.cpu.mem_axi,
wishbone = mem_wb,
base_address = 0))
self.comb += mem_a2w.reset.eq(ResetSignal() | self.cpu.reset)
self.submodules += mem_a2w
litedram_wb = wishbone.Interface(port.data_width)
self.submodules += LiteDRAMWishbone2Native(
wishbone = litedram_wb,
port = port,
base_address = origin)
self.submodules += wishbone.Converter(mem_wb, litedram_wb)
elif self.with_wishbone:
# Wishbone Slave SDRAM interface -------------------------------------------------------
wb_sdram = wishbone.Interface()
self.bus.add_slave("main_ram", wb_sdram)
# L2 Cache -----------------------------------------------------------------------------
if l2_cache_size != 0:
# Insert L2 cache inbetween Wishbone bus and LiteDRAM
l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2
l2_cache_data_width = max(port.data_width, l2_cache_min_data_width)
l2_cache = wishbone.Cache(
cachesize = l2_cache_size//4,
master = wb_sdram,
slave = wishbone.Interface(l2_cache_data_width),
reverse = l2_cache_reverse)
if l2_cache_full_memory_we:
l2_cache = FullMemoryWE()(l2_cache)
self.submodules.l2_cache = l2_cache
litedram_wb = self.l2_cache.slave
else:
litedram_wb = wishbone.Interface(port.data_width)
self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
self.add_config("L2_SIZE", l2_cache_size)
# Wishbone Slave <--> LiteDRAM bridge --------------------------------------------------
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
base_address = self.bus.regions["main_ram"].origin)
def __init__(self, platform, clk_freq, ps7_name, **kwargs):
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
shadow_base=0x00000000,
**kwargs)
# PS7 --------------------------------------------------------------------------------------
self.axi_gp0 = axi_gp0 = axi.AXIInterface(data_width=32,
address_width=32,
id_width=12)
ps7_ddram_pads = platform.request("ps7_ddram")
self.specials += Instance(
ps7_name,
# clk/rst
io_PS_CLK=platform.request("ps7_clk"),
io_PS_PORB=platform.request("ps7_porb"),
io_PS_SRSTB=platform.request("ps7_srstb"),
# mio
io_MIO=platform.request("ps7_mio"),
# ddram
io_DDR_Addr=ps7_ddram_pads.addr,
io_DDR_BankAddr=ps7_ddram_pads.ba,
io_DDR_CAS_n=ps7_ddram_pads.cas_n,
io_DDR_Clk_n=ps7_ddram_pads.ck_n,
io_DDR_Clk=ps7_ddram_pads.ck_p,
io_DDR_CKE=ps7_ddram_pads.cke,
io_DDR_CS_n=ps7_ddram_pads.cs_n,
io_DDR_DM=ps7_ddram_pads.dm,
io_DDR_DQ=ps7_ddram_pads.dq,
io_DDR_DQS_n=ps7_ddram_pads.dqs_n,
io_DDR_DQS=ps7_ddram_pads.dqs_p,
io_DDR_ODT=ps7_ddram_pads.odt,
io_DDR_RAS_n=ps7_ddram_pads.ras_n,
io_DDR_DRSTB=ps7_ddram_pads.reset_n,
io_DDR_WEB=ps7_ddram_pads.we_n,
io_DDR_VRN=ps7_ddram_pads.vrn,
io_DDR_VRP=ps7_ddram_pads.vrp,
# ethernet
i_ENET0_MDIO_I=0,
# sdio0
i_SDIO0_WP=0,
# usb0
i_USB0_VBUS_PWRFAULT=0,
# fabric clk
o_FCLK_CLK0=ClockSignal("sys"),
# axi clk
i_M_AXI_GP0_ACLK=ClockSignal("sys"),
# axi aw
o_M_AXI_GP0_AWVALID=axi_gp0.aw.valid,
i_M_AXI_GP0_AWREADY=axi_gp0.aw.ready,
o_M_AXI_GP0_AWADDR=axi_gp0.aw.addr,
o_M_AXI_GP0_AWBURST=axi_gp0.aw.burst,
o_M_AXI_GP0_AWLEN=axi_gp0.aw.len,
o_M_AXI_GP0_AWSIZE=axi_gp0.aw.size,
o_M_AXI_GP0_AWID=axi_gp0.aw.id,
#o_M_AXI_GP0_AWLOCK =,
#o_M_AXI_GP0_AWPROT =,
#o_M_AXI_GP0_AWCACHE =,
#o_M_AXI_GP0_AWQOS =,
# axi w
o_M_AXI_GP0_WVALID=axi_gp0.w.valid,
o_M_AXI_GP0_WLAST=axi_gp0.w.last,
i_M_AXI_GP0_WREADY=axi_gp0.w.ready,
#o_M_AXI_GP0_WID=,
o_M_AXI_GP0_WDATA=axi_gp0.w.data,
o_M_AXI_GP0_WSTRB=axi_gp0.w.strb,
# axi b
i_M_AXI_GP0_BVALID=axi_gp0.b.valid,
o_M_AXI_GP0_BREADY=axi_gp0.b.ready,
i_M_AXI_GP0_BID=axi_gp0.b.id,
i_M_AXI_GP0_BRESP=axi_gp0.b.resp,
# axi ar
o_M_AXI_GP0_ARVALID=axi_gp0.ar.valid,
i_M_AXI_GP0_ARREADY=axi_gp0.ar.ready,
o_M_AXI_GP0_ARADDR=axi_gp0.ar.addr,
o_M_AXI_GP0_ARBURST=axi_gp0.ar.burst,
o_M_AXI_GP0_ARLEN=axi_gp0.ar.len,
o_M_AXI_GP0_ARID=axi_gp0.ar.id,
#o_M_AXI_GP0_ARLOCK=,
#o_M_AXI_GP0_ARSIZE=,
#o_M_AXI_GP0_ARPROT=,
#o_M_AXI_GP0_ARCACHE=,
#o_M_AXI_GP0_ARQOS=,
# axi r
i_M_AXI_GP0_RVALID=axi_gp0.r.valid,
o_M_AXI_GP0_RREADY=axi_gp0.r.ready,
i_M_AXI_GP0_RLAST=axi_gp0.r.last,
i_M_AXI_GP0_RID=axi_gp0.r.id,
i_M_AXI_GP0_RRESP=axi_gp0.r.resp,
i_M_AXI_GP0_RDATA=axi_gp0.r.data,
)
platform.add_ip(os.path.join("ip", ps7_name + ".xci"))
# AXI to Wishbone --------------------------------------------------------------------------
self.wb_gp0 = wb_gp0 = wishbone.Interface()
axi2wishbone = axi.AXI2Wishbone(axi_gp0,
wb_gp0,
base_address=0x43c00000)
self.submodules += axi2wishbone
self.add_wb_master(wb_gp0)
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(4)
mem_dw, mmio_dw = AXI_DATA_WIDTHS[self.variant]
self.mem_axi = mem_axi = axi.AXIInterface(data_width= mem_dw, address_width=32, id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4)
self.mmio_wb = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8))
self.periph_buses = [mmio_wb]
self.memory_buses = [mem_axi]
# # #
self.cpu_params = dict(
# clock, reset
i_clock=ClockSignal(),
i_reset=ResetSignal() | self.reset,
# debug (ignored)
#o_debug_clockeddmi_dmi_req_ready = ,
i_debug_clockeddmi_dmi_req_valid = 0,
i_debug_clockeddmi_dmi_req_bits_addr = 0,
i_debug_clockeddmi_dmi_req_bits_data = 0,
i_debug_clockeddmi_dmi_req_bits_op = 0,
i_debug_clockeddmi_dmi_resp_ready = 0,
#o_debug_clockeddmi_dmi_resp_valid = ,
#o_debug_clockeddmi_dmi_resp_bits_data = ,
#o_debug_clockeddmi_dmi_resp_bits_resp = ,
i_debug_clockeddmi_dmiClock = 0,
i_debug_clockeddmi_dmiReset = 0,
#o_debug_ndreset = ,
#o_debug_dmactive = ,
# irq
i_interrupts=self.interrupt,
# axi memory (L1-cached)
i_mem_axi4_0_aw_ready = mem_axi.aw.ready,
o_mem_axi4_0_aw_valid = mem_axi.aw.valid,
o_mem_axi4_0_aw_bits_id = mem_axi.aw.id,
o_mem_axi4_0_aw_bits_addr = mem_axi.aw.addr,
o_mem_axi4_0_aw_bits_len = mem_axi.aw.len,
o_mem_axi4_0_aw_bits_size = mem_axi.aw.size,
o_mem_axi4_0_aw_bits_burst = mem_axi.aw.burst,
o_mem_axi4_0_aw_bits_lock = mem_axi.aw.lock,
o_mem_axi4_0_aw_bits_cache = mem_axi.aw.cache,
o_mem_axi4_0_aw_bits_prot = mem_axi.aw.prot,
o_mem_axi4_0_aw_bits_qos = mem_axi.aw.qos,
i_mem_axi4_0_w_ready = mem_axi.w.ready,
o_mem_axi4_0_w_valid = mem_axi.w.valid,
o_mem_axi4_0_w_bits_data = mem_axi.w.data,
o_mem_axi4_0_w_bits_strb = mem_axi.w.strb,
o_mem_axi4_0_w_bits_last = mem_axi.w.last,
o_mem_axi4_0_b_ready = mem_axi.b.ready,
i_mem_axi4_0_b_valid = mem_axi.b.valid,
i_mem_axi4_0_b_bits_id = mem_axi.b.id,
i_mem_axi4_0_b_bits_resp = mem_axi.b.resp,
i_mem_axi4_0_ar_ready = mem_axi.ar.ready,
o_mem_axi4_0_ar_valid = mem_axi.ar.valid,
o_mem_axi4_0_ar_bits_id = mem_axi.ar.id,
o_mem_axi4_0_ar_bits_addr = mem_axi.ar.addr,
o_mem_axi4_0_ar_bits_len = mem_axi.ar.len,
o_mem_axi4_0_ar_bits_size = mem_axi.ar.size,
o_mem_axi4_0_ar_bits_burst = mem_axi.ar.burst,
o_mem_axi4_0_ar_bits_lock = mem_axi.ar.lock,
o_mem_axi4_0_ar_bits_cache = mem_axi.ar.cache,
o_mem_axi4_0_ar_bits_prot = mem_axi.ar.prot,
o_mem_axi4_0_ar_bits_qos = mem_axi.ar.qos,
o_mem_axi4_0_r_ready = mem_axi.r.ready,
i_mem_axi4_0_r_valid = mem_axi.r.valid,
i_mem_axi4_0_r_bits_id = mem_axi.r.id,
i_mem_axi4_0_r_bits_data = mem_axi.r.data,
i_mem_axi4_0_r_bits_resp = mem_axi.r.resp,
i_mem_axi4_0_r_bits_last = mem_axi.r.last,
# axi mmio (not cached)
i_mmio_axi4_0_aw_ready = mmio_axi.aw.ready,
o_mmio_axi4_0_aw_valid = mmio_axi.aw.valid,
o_mmio_axi4_0_aw_bits_id = mmio_axi.aw.id,
o_mmio_axi4_0_aw_bits_addr = mmio_axi.aw.addr,
o_mmio_axi4_0_aw_bits_len = mmio_axi.aw.len,
o_mmio_axi4_0_aw_bits_size = mmio_axi.aw.size,
o_mmio_axi4_0_aw_bits_burst = mmio_axi.aw.burst,
o_mmio_axi4_0_aw_bits_lock = mmio_axi.aw.lock,
o_mmio_axi4_0_aw_bits_cache = mmio_axi.aw.cache,
o_mmio_axi4_0_aw_bits_prot = mmio_axi.aw.prot,
o_mmio_axi4_0_aw_bits_qos = mmio_axi.aw.qos,
i_mmio_axi4_0_w_ready = mmio_axi.w.ready,
o_mmio_axi4_0_w_valid = mmio_axi.w.valid,
o_mmio_axi4_0_w_bits_data = mmio_axi.w.data,
o_mmio_axi4_0_w_bits_strb = mmio_axi.w.strb,
o_mmio_axi4_0_w_bits_last = mmio_axi.w.last,
o_mmio_axi4_0_b_ready = mmio_axi.b.ready,
i_mmio_axi4_0_b_valid = mmio_axi.b.valid,
i_mmio_axi4_0_b_bits_id = mmio_axi.b.id,
i_mmio_axi4_0_b_bits_resp = mmio_axi.b.resp,
i_mmio_axi4_0_ar_ready = mmio_axi.ar.ready,
o_mmio_axi4_0_ar_valid = mmio_axi.ar.valid,
o_mmio_axi4_0_ar_bits_id = mmio_axi.ar.id,
o_mmio_axi4_0_ar_bits_addr = mmio_axi.ar.addr,
o_mmio_axi4_0_ar_bits_len = mmio_axi.ar.len,
o_mmio_axi4_0_ar_bits_size = mmio_axi.ar.size,
o_mmio_axi4_0_ar_bits_burst = mmio_axi.ar.burst,
o_mmio_axi4_0_ar_bits_lock = mmio_axi.ar.lock,
o_mmio_axi4_0_ar_bits_cache = mmio_axi.ar.cache,
o_mmio_axi4_0_ar_bits_prot = mmio_axi.ar.prot,
o_mmio_axi4_0_ar_bits_qos = mmio_axi.ar.qos,
o_mmio_axi4_0_r_ready = mmio_axi.r.ready,
i_mmio_axi4_0_r_valid = mmio_axi.r.valid,
i_mmio_axi4_0_r_bits_id = mmio_axi.r.id,
i_mmio_axi4_0_r_bits_data = mmio_axi.r.data,
i_mmio_axi4_0_r_bits_resp = mmio_axi.r.resp,
i_mmio_axi4_0_r_bits_last = mmio_axi.r.last,
)
# adapt axi interfaces to wishbone
# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb,
base_address=0))
self.comb += mmio_a2w.reset.eq(ResetSignal() | self.reset)
self.submodules += mmio_a2w
# add verilog sources
self.add_sources(platform, variant)
def __init__(self, platform, cpu_reset_addr, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
assert cpu_reset_addr == 0x10000000, "cpu_reset_addr hardcoded in Chisel elaboration!"
self.platform = platform
self.variant = variant
self.reset = Signal()
self.interrupt = Signal(4)
self.mem_axi = mem_axi = axi.AXIInterface(
data_width=64, address_width=32, id_width=4)
self.mmio_axi = mmio_axi = axi.AXIInterface(
data_width=64, address_width=32, id_width=4)
self.mem_wb = mem_wb = wishbone.Interface(data_width=64, adr_width=29)
self.mmio_wb = mmio_wb = wishbone.Interface(data_width=64, adr_width=29)
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
# # #
self.specials += Instance("ExampleRocketSystem",
# clock, reset
i_clock=ClockSignal(),
i_reset=ResetSignal() | self.reset,
# debug (ignored)
#o_debug_clockeddmi_dmi_req_ready=,
i_debug_clockeddmi_dmi_req_valid=0,
i_debug_clockeddmi_dmi_req_bits_addr=0,
i_debug_clockeddmi_dmi_req_bits_data=0,
i_debug_clockeddmi_dmi_req_bits_op=0,
i_debug_clockeddmi_dmi_resp_ready=0,
#o_debug_clockeddmi_dmi_resp_valid=,
#o_debug_clockeddmi_dmi_resp_bits_data=,
#o_debug_clockeddmi_dmi_resp_bits_resp=,
i_debug_clockeddmi_dmiClock=0,
i_debug_clockeddmi_dmiReset=0,
#o_debug_ndreset=,
#o_debug_dmactive=,
# irq
i_interrupts=self.interrupt,
# axi memory (L1-cached)
i_mem_axi4_0_aw_ready=mem_axi.aw.ready,
o_mem_axi4_0_aw_valid=mem_axi.aw.valid,
o_mem_axi4_0_aw_bits_id=mem_axi.aw.id,
o_mem_axi4_0_aw_bits_addr=mem_axi.aw.addr,
o_mem_axi4_0_aw_bits_len=mem_axi.aw.len,
o_mem_axi4_0_aw_bits_size=mem_axi.aw.size,
o_mem_axi4_0_aw_bits_burst=mem_axi.aw.burst,
o_mem_axi4_0_aw_bits_lock=mem_axi.aw.lock,
o_mem_axi4_0_aw_bits_cache=mem_axi.aw.cache,
o_mem_axi4_0_aw_bits_prot=mem_axi.aw.prot,
o_mem_axi4_0_aw_bits_qos=mem_axi.aw.qos,
i_mem_axi4_0_w_ready=mem_axi.w.ready,
o_mem_axi4_0_w_valid=mem_axi.w.valid,
o_mem_axi4_0_w_bits_data=mem_axi.w.data,
o_mem_axi4_0_w_bits_strb=mem_axi.w.strb,
o_mem_axi4_0_w_bits_last=mem_axi.w.last,
o_mem_axi4_0_b_ready=mem_axi.b.ready,
i_mem_axi4_0_b_valid=mem_axi.b.valid,
i_mem_axi4_0_b_bits_id=mem_axi.b.id,
i_mem_axi4_0_b_bits_resp=mem_axi.b.resp,
i_mem_axi4_0_ar_ready=mem_axi.ar.ready,
o_mem_axi4_0_ar_valid=mem_axi.ar.valid,
o_mem_axi4_0_ar_bits_id=mem_axi.ar.id,
o_mem_axi4_0_ar_bits_addr=mem_axi.ar.addr,
o_mem_axi4_0_ar_bits_len=mem_axi.ar.len,
o_mem_axi4_0_ar_bits_size=mem_axi.ar.size,
o_mem_axi4_0_ar_bits_burst=mem_axi.ar.burst,
o_mem_axi4_0_ar_bits_lock=mem_axi.ar.lock,
o_mem_axi4_0_ar_bits_cache=mem_axi.ar.cache,
o_mem_axi4_0_ar_bits_prot=mem_axi.ar.prot,
o_mem_axi4_0_ar_bits_qos=mem_axi.ar.qos,
o_mem_axi4_0_r_ready=mem_axi.r.ready,
i_mem_axi4_0_r_valid=mem_axi.r.valid,
i_mem_axi4_0_r_bits_id=mem_axi.r.id,
i_mem_axi4_0_r_bits_data=mem_axi.r.data,
i_mem_axi4_0_r_bits_resp=mem_axi.r.resp,
i_mem_axi4_0_r_bits_last=mem_axi.r.last,
# axi mmio (not cached)
i_mmio_axi4_0_aw_ready=mmio_axi.aw.ready,
o_mmio_axi4_0_aw_valid=mmio_axi.aw.valid,
o_mmio_axi4_0_aw_bits_id=mmio_axi.aw.id,
o_mmio_axi4_0_aw_bits_addr=mmio_axi.aw.addr,
o_mmio_axi4_0_aw_bits_len=mmio_axi.aw.len,
o_mmio_axi4_0_aw_bits_size=mmio_axi.aw.size,
o_mmio_axi4_0_aw_bits_burst=mmio_axi.aw.burst,
o_mmio_axi4_0_aw_bits_lock=mmio_axi.aw.lock,
o_mmio_axi4_0_aw_bits_cache=mmio_axi.aw.cache,
o_mmio_axi4_0_aw_bits_prot=mmio_axi.aw.prot,
o_mmio_axi4_0_aw_bits_qos=mmio_axi.aw.qos,
i_mmio_axi4_0_w_ready=mmio_axi.w.ready,
o_mmio_axi4_0_w_valid=mmio_axi.w.valid,
o_mmio_axi4_0_w_bits_data=mmio_axi.w.data,
o_mmio_axi4_0_w_bits_strb=mmio_axi.w.strb,
o_mmio_axi4_0_w_bits_last=mmio_axi.w.last,
o_mmio_axi4_0_b_ready=mmio_axi.b.ready,
i_mmio_axi4_0_b_valid=mmio_axi.b.valid,
i_mmio_axi4_0_b_bits_id=mmio_axi.b.id,
i_mmio_axi4_0_b_bits_resp=mmio_axi.b.resp,
i_mmio_axi4_0_ar_ready=mmio_axi.ar.ready,
o_mmio_axi4_0_ar_valid=mmio_axi.ar.valid,
o_mmio_axi4_0_ar_bits_id=mmio_axi.ar.id,
o_mmio_axi4_0_ar_bits_addr=mmio_axi.ar.addr,
o_mmio_axi4_0_ar_bits_len=mmio_axi.ar.len,
o_mmio_axi4_0_ar_bits_size=mmio_axi.ar.size,
o_mmio_axi4_0_ar_bits_burst=mmio_axi.ar.burst,
o_mmio_axi4_0_ar_bits_lock=mmio_axi.ar.lock,
o_mmio_axi4_0_ar_bits_cache=mmio_axi.ar.cache,
o_mmio_axi4_0_ar_bits_prot=mmio_axi.ar.prot,
o_mmio_axi4_0_ar_bits_qos=mmio_axi.ar.qos,
o_mmio_axi4_0_r_ready=mmio_axi.r.ready,
i_mmio_axi4_0_r_valid=mmio_axi.r.valid,
i_mmio_axi4_0_r_bits_id=mmio_axi.r.id,
i_mmio_axi4_0_r_bits_data=mmio_axi.r.data,
i_mmio_axi4_0_r_bits_resp=mmio_axi.r.resp,
i_mmio_axi4_0_r_bits_last=mmio_axi.r.last,
)
# adapt axi interfaces to wishbone
mem_a2w = ResetInserter()(
axi.AXI2Wishbone(mem_axi, mem_wb, base_address=0))
mmio_a2w = ResetInserter()(
axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
self.comb += [
mem_a2w.reset.eq(ResetSignal() | self.reset),
mmio_a2w.reset.eq(ResetSignal() | self.reset),
]
# down-convert wishbone from 64 to 32 bit data width
mem_dc = wishbone.Converter(mem_wb, ibus)
mmio_dc = wishbone.Converter(mmio_wb, dbus)
self.submodules += mem_a2w, mem_dc, mmio_a2w, mmio_dc
# add verilog sources
self.add_sources(platform)
def add_axi_to_wishbone(self, axi_port, base_address=0x43c00000):
wb = wishbone.Interface()
axi2wishbone = axi.AXI2Wishbone(axi_port, wb, base_address)
self.submodules += axi2wishbone
self.add_wb_master(wb)
def __init__(self, f_sys, f_sample, **kwargs):
'''
f_sys: system clock frequency (wishbone)
f_sample: ADC sampling clock frequency (provided by )
'''
SoCCore.__init__(
self,
clk_freq=f_sys,
cpu_type="zynq7000",
csr_data_width=32,
# csr_address_width=16,
with_uart=False,
with_timer=False,
integrated_rom_size=0,
integrated_main_ram_size=0,
integrated_sram_size=0,
ident="Zedboard RF vector volt-meter",
ident_version=True,
add_reset=False,
**kwargs)
for c in ZedVvm.csr_peripherals:
self.add_csr(c)
p = self.platform
p.add_extension([
(
"PMODA_SPI",
0,
Subsignal("cs_n", Pins("pmoda:5")),
Subsignal("clk", Pins("pmoda:6")),
Subsignal("mosi", Pins("pmoda:7")),
# OLED does not have a MISO pin :(
IOStandard("LVCMOS33")),
("PMODA_GPIO", 0,
Subsignal("gpio",
Pins("pmoda:0 pmoda:1 pmoda:2 pmoda:3 pmoda:4")),
IOStandard("LVCMOS33"))
])
# FPGA identification
self.submodules.dna = dna.DNA()
# Add Zynq configuration IP
self.cpu.set_ps7_xci("ip/processing_system7_0.xci")
# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default)
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(axi=self.cpu.add_axi_gp_master(),
wishbone=wb_gp0,
base_address=0x43c00000)
self.add_wb_master(wb_gp0)
# ----------------------------
# FPGA clock and reset generation
# ----------------------------
# Delay the CSR reset signal such that wishbone can send an ACK
# to the Zynq PS, which would freeze up otherwise
csr_reset_active = Signal()
self.sync += If(self.ctrl.reset, csr_reset_active.eq(1))
self.submodules.rst_delay = WaitTimer(2**16) # 655 us
self.comb += self.rst_delay.wait.eq(csr_reset_active)
self.submodules.crg = _CRG(
p,
f_sys,
f_sample,
[
p.request('user_btn_u'), # UP button on zedboard
self.rst_delay.done # ctrl_reset csr (delayed by 100 ms)
])
# ----------------------------
# LTC LVDS driver on FMC-LPC
# ----------------------------
p.add_extension(ltc_pads)
# LTCPhy will recover ADC clock and drive `sample` clock domain
self.submodules.lvds = LTCPhy(p, f_sys, f_sample)
# tell vivado that sys_clk and sampl_clk are asynchronous
# p.add_platform_command('create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]')
# p.add_platform_command('set_input_jitter clk_fpga_0 0.3')
clk_str = f'create_clock -period {1e9 / f_sample} -waveform {{{{0.000 {1e9 / 2 / f_sample}}}}} [get_nets sample_clk]'
print(clk_str)
p.add_platform_command(clk_str)
p.add_false_path_constraints(self.lvds.pads_dco, self.cpu.cd_ps7.clk,
self.lvds.cd_sample.clk)
# p.add_platform_command('set_clock_groups -asynchronous -group [get_clocks {{bufr_0_clk}}] -group [get_clocks {{clk_fpga_0}}]')
# ----------------------------
# SPI bit-bang master
# ----------------------------
spi_pads = p.request("LTC_SPI")
self.submodules.spi = SPIMaster(spi_pads)
# ----------------------------
# 4 x Acquisition memory for ADC data
# ----------------------------
mems = []
for i, sample_out in enumerate(self.lvds.sample_outs):
mem = Memory(14, 4096)
mems.append(mem)
self.specials += mem
self.submodules.sample_ram = wishbone.SRAM(mem, read_only=True)
self.register_mem(
"sample{}".format(i),
0x10000000 + i * 0x01000000, # [bytes]
self.sample_ram.bus,
mem.depth * 4 # [bytes]
)
# ----------------------------
# DSO Trigger logic
# ----------------------------
self.submodules.acq = Acquisition(mems,
self.lvds.sample_outs,
N_BITS=14)
self.specials += MultiReg(p.request('user_btn_c'), self.acq.trigger,
'sample')
# ----------------------------
# Vector volt-meter
# ----------------------------
VVM_DSP.add_sources(p)
self.submodules.vvm = VVM_DSP(self.lvds.sample_outs)
self.vvm.add_csr(f_sys, p)
# -------------------------------------------------------
# OLED display / PS GPIOs / Si570
# -------------------------------------------------------
# Forward the internal PS EMIO to actual pads in the real world
# SPI0, SS0 from PS through EMIO to PMODA
self.cpu.add_emio_spi(p.request("PMODA_SPI"), n=0)
# GPIOs to PMODA
self.cpu.add_emio_gpio(p.request("PMODA_GPIO").gpio)
# On board tiny OLED display
p.add_oled(self, SPI_N=0, SS_N=1, DC_GPIO=8, RST_GPIO=9)
# Si570 I2C module
self.submodules.si570 = Si570(p, self)
