def __init__(self, device="85F", sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = ecpix5.Platform(device=device, toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECPIX-5", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), rx_delay=0e-9) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- leds_pads = [] for i in range(4): rgb_led_pads = platform.request("rgb_led", i) self.comb += [getattr(rgb_led_pads, n).eq(1) for n in "gb"] # Disable Green/Blue Leds. leds_pads += [getattr(rgb_led_pads, n) for n in "r"] self.submodules.leds = LedChaser(pads=Cat(leds_pads), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): platform = ecpix5.Platform(toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECPIX-5", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:2"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), rx_delay=0e-9) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Leds (Disable...) ------------------------------------------------------------------------ for i in range(4): rgb_led_pads = platform.request("rgb_led", i) for c in "rgb": self.comb += getattr(rgb_led_pads, c).eq(1)
def __init__(self, device="85F", sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, with_led_chaser=True, **kwargs): platform = ecpix5.Platform(device=device, toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECPIX-5", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K256M16(sys_clk_freq, "1:2"), l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), rx_delay=0e-9) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # HDMI ------------------------------------------------------------------------------------- if with_video_terminal or with_video_framebuffer: # PHY + IT6613 I2C initialization. hdmi_pads = platform.request("hdmi") self.submodules.videophy = VideoDVIPHY(hdmi_pads, clock_domain="init") self.submodules.videoi2c = I2CMaster(hdmi_pads) # I2C initialization adapted from https://github.com/ultraembedded/ecpix-5 # Copyright (c) 2020 https://github.com/ultraembedded # Adapted from C to Python. REG_TX_SW_RST = 0x04 B_ENTEST = (1 << 7) B_REF_RST = (1 << 5) B_AREF_RST = (1 << 4) B_VID_RST = (1 << 3) B_AUD_RST = (1 << 2) B_HDMI_RST = (1 << 1) B_HDCP_RST = (1 << 0) REG_TX_AFE_DRV_CTRL = 0x61 B_AFE_DRV_PWD = (1 << 5) B_AFE_DRV_RST = (1 << 4) B_AFE_DRV_PDRXDET = (1 << 2) B_AFE_DRV_TERMON = (1 << 1) B_AFE_DRV_ENCAL = (1 << 0) REG_TX_AFE_XP_CTRL = 0x62 B_AFE_XP_GAINBIT = (1 << 7) B_AFE_XP_PWDPLL = (1 << 6) B_AFE_XP_ENI = (1 << 5) B_AFE_XP_ER0 = (1 << 4) B_AFE_XP_RESETB = (1 << 3) B_AFE_XP_PWDI = (1 << 2) B_AFE_XP_DEI = (1 << 1) B_AFE_XP_DER = (1 << 0) REG_TX_AFE_ISW_CTRL = 0x63 B_AFE_RTERM_SEL = (1 << 7) B_AFE_IP_BYPASS = (1 << 6) M_AFE_DRV_ISW = (7 << 3) O_AFE_DRV_ISW = 3 B_AFE_DRV_ISWK = 7 REG_TX_AFE_IP_CTRL = 0x64 B_AFE_IP_GAINBIT = (1 << 7) B_AFE_IP_PWDPLL = (1 << 6) M_AFE_IP_CKSEL = (3 << 4) O_AFE_IP_CKSEL = 4 B_AFE_IP_ER0 = (1 << 3) B_AFE_IP_RESETB = (1 << 2) B_AFE_IP_ENC = (1 << 1) B_AFE_IP_EC1 = (1 << 0) REG_TX_HDMI_MODE = 0xC0 B_TX_HDMI_MODE = 1 B_TX_DVI_MODE = 0 REG_TX_GCP = 0xC1 B_CLR_AVMUTE = 0 B_SET_AVMUTE = 1 B_TX_SETAVMUTE = (1 << 0) B_BLUE_SCR_MUTE = (1 << 1) B_NODEF_PHASE = (1 << 2) B_PHASE_RESYNC = (1 << 3) self.videoi2c.add_init( addr=0x4c, init=[ # Reset. (REG_TX_SW_RST, B_REF_RST | B_VID_RST | B_AUD_RST | B_AREF_RST | B_HDCP_RST), (REG_TX_SW_RST, 0), # Select DVI Mode. (REG_TX_HDMI_MODE, B_TX_DVI_MODE), # Configure Clks. (REG_TX_SW_RST, B_AUD_RST | B_AREF_RST | B_HDCP_RST), (REG_TX_AFE_DRV_CTRL, B_AFE_DRV_RST), (REG_TX_AFE_XP_CTRL, 0x18), (REG_TX_AFE_ISW_CTRL, 0x10), (REG_TX_AFE_IP_CTRL, 0x0C), # Enable Clks. (REG_TX_AFE_DRV_CTRL, 0), # Enable Video. (REG_TX_GCP, 0), ]) # Video Terminal/Framebuffer. if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="init") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="init") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: leds_pads = [] for i in range(4): rgb_led_pads = platform.request("rgb_led", i) self.comb += [getattr(rgb_led_pads, n).eq(1) for n in "gb"] # Disable Green/Blue Leds. leds_pads += [getattr(rgb_led_pads, n) for n in "r"] self.submodules.leds = LedChaser(pads=Cat(leds_pads), sys_clk_freq=sys_clk_freq)