def main():
parser = argparse.ArgumentParser(description="LitePCIe SoC on FK33")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--driver",
action="store_true",
help="Generate LitePCIe driver")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
parser.add_argument("--speed",
default="gen2",
help="PCIe speed: gen2 (default) or gen3")
parser.add_argument("--nlanes",
default=4,
help="PCIe lanes: 4 (default) or 8")
args = parser.parse_args()
platform = fk33.Platform()
soc = LitePCIeSoC(platform, speed=args.speed, nlanes=int(args.nlanes))
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
platform = fk33.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "jtag_uart" # Defaults to JTAG-UART.
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on FK33",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = USPHBMPCIEPHY(
platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
# Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(
self.pcie_phy, max_pending_requests=8)
# Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_constant("DMA_CHANNELS", 1)
# MSI
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(125e6),
with_led_chaser=True,
with_pcie=False,
with_hbm=False,
**kwargs):
platform = fk33.Platform()
if with_hbm:
assert 225e6 <= sys_clk_freq <= 450e6
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover-UART.
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on FK33",
**kwargs)
# JTAGBone --------------------------------------------------------------------------------
self.add_jtagbone(
chain=2) # Chain 1 already used by HBM2 debug probes.
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_hbm)
# HBM --------------------------------------------------------------------------------------
if with_hbm:
# Add HBM Core.
self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(
USPHBM2(platform))
# Get HBM .xci.
os.system(
"wget https://github.com/litex-hub/litex-boards/files/8178874/hbm_0.xci.txt"
)
os.makedirs("ip/hbm", exist_ok=True)
os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci")
# Connect four of the HBM's AXI interfaces to the main bus of the SoC.
for i in range(4):
axi_hbm = hbm.axi[i]
axi_lite_hbm = AXILiteInterface(data_width=256,
address_width=33)
self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm)
self.bus.add_slave(f"hbm{i}", axi_lite_hbm,
SoCRegion(origin=0x4000_0000 +
0x1000_0000 * i,
size=0x1000_0000)) # 256MB.
# Link HBM2 channel 0 as main RAM
self.bus.add_region("main_ram",
SoCRegion(origin=0x4000_0000,
size=0x1000_0000,
linker=True)) # 256MB.
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
assert self.csr_data_width == 32
# PHY
self.submodules.pcie_phy = USPHBMPCIEPHY(
platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
# Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(
self.pcie_phy, max_pending_requests=8)
# Wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(
self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_bridge.wishbone)
# DMA0
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_buffering=True,
buffering_depth=1024,
with_loopback=True)
self.add_constant("DMA_CHANNELS", 1)
# MSI
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)