def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore -----------------------------------------------------------------_----------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="diamond",
integrated_rom_size=0x8000,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
**kwargs)
# crg
crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41J256M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self):
platform = trellisboard.Platform()
# BenchPHY ---------------------------------------------------------------------------------
BaseSoC.__init__(self,
sys_clk_freq=int(100e6),
cpu_type=None,
integrated_main_ram_size=0x100)
# SDCard on PMODA with Digilent's Pmod TPH2 + Pmod MicroSD --------------------------------
_sdcard_pmod_ios = [(
"sdcard_pmoda",
0,
Subsignal("clk", Pins("pmoda:3")),
Subsignal("cmd", Pins("pmoda:1"), Misc("PULLMODE=UP")),
Subsignal("data", Pins("pmoda:2 pmoda:4 pmoda:5 pmoda:0"),
Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
)]
self.platform.add_extension(_sdcard_pmod_ios)
from litesdcard.phy import SDPHY
self.submodules.sd_phy = SDPHY(self.platform.request("sdcard_pmoda"),
platform.device, self.clk_freq)
self.add_csr("sd_phy")
# Send a command with button to verify timings ---------------------------------------------
self.comb += [
If(
self.platform.request("user_btn", 3),
self.sd_phy.cmdw.sink.valid.eq(1),
self.sd_phy.cmdw.sink.data.eq(0x5a),
)
]
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
with_led_chaser=True,
with_pmod_gpio=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(trellisboard.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(12)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
self.add_ram("firmware_ram", 0x20000000, 0x10000)
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41J256M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
with_video_terminal=False,
with_video_framebuffer=False,
with_led_chaser=True,
with_pmod_gpio=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# HDMI -------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
# PHY + TP410 I2C initialization.
hdmi_pads = platform.request("hdmi")
self.submodules.videophy = VideoDVIPHY(hdmi_pads,
clock_domain="init")
self.submodules.videoi2c = I2CMaster(hdmi_pads)
self.videoi2c.add_init(
addr=0x38,
init=[(0x08, 0x35
) # CTL_1_MODE: Normal operation, 24-bit, HSYNC/VSYNC.
])
# Video Terminal/Framebuffer.
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(trellisboard.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self,
variant="minimal",
with_sampler=False,
with_analyzer=False,
host_ip="192.168.1.100",
host_udp_port=2000):
platform = trellisboard.Platform()
# BenchSoC ---------------------------------------------------------------------------------
bench_kwargs = {
"minimal": dict(cpu_variant="minimal",
integrated_main_ram_size=0x1000),
"standard": dict(),
}[variant]
BaseSoC.__init__(self,
sys_clk_freq=int(75e6),
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
**bench_kwargs)
# SDCard on PMODA with Digilent's Pmod TPH2 + Pmod MicroSD --------------------------------
_sdcard_pmod_ios = [(
"sdcard_pmoda",
0,
Subsignal("clk", Pins("pmoda:3")),
Subsignal("cmd", Pins("pmoda:1"), Misc("PULLMODE=UP")),
Subsignal("data", Pins("pmoda:2 pmoda:4 pmoda:5 pmoda:0"),
Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
)]
self.platform.add_extension(_sdcard_pmod_ios)
self.add_sdcard("sdcard_pmoda")
if with_sampler or with_analyzer:
# Etherbone ----------------------------------------------------------------------------
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
if with_sampler:
# PMODB Sampler (connected to PmodTPH2 with Pmode Cable Kit) ---------------------------
_la_pmod_ios = [("la_pmod", 0,
Pins("pmodb:0 pmodb:1 pmodb:2 pmodb:3",
"pmodb:4 pmodb:5 pmodb:6 pmodb:7"),
IOStandard("LVCMOS33"))]
self.platform.add_extension(_la_pmod_ios)
self.submodules.sampler = Sampler(self.platform.request("la_pmod"))
self.add_csr("sampler")
# UDPStreamer --------------------------------------------------------------------------
from liteeth.common import convert_ip
from liteeth.frontend.stream import LiteEthStream2UDPTX
udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8)
udp_streamer = LiteEthStream2UDPTX(ip_address=convert_ip(host_ip),
udp_port=host_udp_port,
fifo_depth=1024)
udp_streamer = ClockDomainsRenamer("eth_tx")(udp_streamer)
self.submodules += udp_streamer
udp_cdc = stream.ClockDomainCrossing([("data", 8)], "sys",
"eth_tx")
self.submodules += udp_cdc
# Sampler/UDPStreamer flow -------------------------------------------------------------
self.comb += self.sampler.source.connect(udp_cdc.sink)
self.comb += udp_cdc.source.connect(udp_streamer.sink)
self.comb += udp_streamer.source.connect(udp_port.sink)
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [
self.sdphy.sdpads,
self.sdphy.cmdw.sink,
self.sdphy.cmdr.sink,
self.sdphy.cmdr.source,
self.sdphy.dataw.sink,
self.sdphy.dataw.stop,
self.sdphy.dataw.crc.source,
self.sdphy.dataw.status.status,
self.sdphy.datar.sink,
self.sdphy.datar.source,
self.sdphy.clocker.ce,
self.sdphy.clocker.stop,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=2048,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
sys_clk_freq=int(75e6),
cpu_count=1,
with_ethernet=False,
**kwargs):
VexRiscvSMP.litedram_width = 128
VexRiscvSMP.ibus_width = 64
VexRiscvSMP.dbus_width = 64
VexRiscvSMP.coherent_dma = True
platform = trellisboard.Platform(toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_size"] = 0x10000
kwargs["csr_data_width"] = 8
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_cls=VexRiscvSMP,
cpu_variant="default",
**kwargs)
self.add_constant("config_cpu_count", cpu_count) # for dts generation
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0C00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(pads=PHYPadsReducer(
platform.request("ddram"), [0, 1]),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True,
controller_settings=ControllerSettings(
cmd_buffer_buffered=False,
with_auto_precharge=False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
