def __init__(self, Path, Prefix, Monitors, Print=False, Bwen=True):
self.Prefix = Prefix
self.Path = Path
self.Active = False
self.Print = Print
self.Bwen = Bwen
self.Ram = {}
Full = '%s.%s%s' % (self.Path, self.Prefix, 'wdata')
Full = veri.peek(Full)
self.dataWidth = len(Full)
self.strD = '%%0%dx' % (self.dataWidth / 4)
Full = '%s.%s%s' % (self.Path, self.Prefix, 'addr')
Full = veri.peek(Full)
Len = len(Full)
self.addrWidth = Len
Monitors.append(self)
if self.Bwen:
Bweb = self.peeks('bwen')
else:
Bweb = 0
logs.log_info('ramMonitor #%d setup %s dataw=%d addrw=%d bweb=%s' %
(ramMonitorClass.runnum, self.Prefix, self.dataWidth,
self.addrWidth, Bweb))
ramMonitorClass.runnum += 1
def reportNetTable(Mod):
global reported
if reported: return
for Key in Mod.netTable.keys():
List = Mod.netTable[Key]
logs.log_info('NETABLE %s %s' % (Key, List), 2)
reported = True
def sequence(TestName):
Seq = logs.bin2string(TestName)
seq.readfile(Seq)
logs.setVar('sequence', Seq)
Dir = os.path.dirname(Seq)
logs.setVar('testsdir', Dir)
logs.log_info('SEQUENCE %d' % len(seq.Sequence))
def help_main(Env):
Mod = Env.Current
buildTranslation(Mod)
logs.log_info('translation has %d members' % (len(TRANSLATIONS.keys())))
Insts = list(Mod.insts.keys())
# gatherAssigns(Mod)
for Inst in Insts:
Obj = Mod.insts[Inst]
Type = Obj.Type
logs.log_info('inst %s %s' % (Inst, Type))
Del = dealType(Type, Inst, Obj, Mod)
if Del:
Mod.insts.pop(Inst)
Fout = open('%s.rtl0' % Mod.Module, 'w')
Mod.dump_verilog(Fout)
Fout.close()
gatherAlwayses(Mod)
Fout = open('%s.rtl1' % Mod.Module, 'w')
Mod.dump_verilog(Fout)
Fout.close()
gatherExpressions(Mod)
Fout = open('%s.rtl2' % Mod.Module, 'w')
Mod.dump_verilog(Fout)
Fout.close()
def add_module(Key):
global Current, ModuleStuffs
List = DataBase[Key]
Module = List[1][0]
Current = module_class(Module)
Modules[Module] = Current
logs.log_info('addmodule %s (%s)' % (Module, Modules.keys()))
if len(List) == 5:
Lhead = DataBase[List[2]]
Lbody = DataBase[List[3]]
Lparams = []
elif len(List) == 6:
Lparams = DataBase[List[2]]
Lhead = DataBase[List[3]]
Lbody = DataBase[List[4]]
elif len(List) == 3:
if (List[0][1] == 'define'):
Var = List[1][0]
Expr = get_expr(List[2])
add_module_define(Var, Expr)
else:
logs.log_err('dont know to deal with %d %s' % (len(List), List))
return
if (len(Lparams) > 0):
add_module_params(Lparams)
if (len(Lhead) > 1):
add_module_header(Lhead)
if (len(Lbody) > 0):
ModuleStuffs = [Lbody]
while (ModuleStuffs != []):
add_module_stuff()
def reading(self):
if len(self.arqueue) > 4:
self.force('arready', 0)
elif self.peek('arvalid') == 1:
self.force('arready', 1)
arid = self.peek('arid')
arburst = self.peek('arburst')
araddr = self.peek('araddr')
logs.log_info('>>>>>>>> %s %x' % (arburst, araddr))
arlen = self.peek('arlen')
arsize = self.peek('arsize')
self.arqueue.append((arburst, araddr, arlen, arsize))
self.rqueue.append(('wait', self.WAITREAD, 0))
for ii in range(arlen):
self.readQueue(arlen, ii, arburst, arsize, araddr, arid, 0)
self.readQueue(arlen, arlen, arburst, arsize, araddr, arid, 1)
self.rqueue.append('pop')
LastAddr = (araddr + (arlen + 1) * (1 << arsize)) - 1
LastPage = LastAddr & 0xffffe000
FirstPage = araddr & 0xffffe000
if (FirstPage != LastPage):
logs.log_error(
'slave %s CROSSING 4K read araddr=%x arlen=%x arsize=%x' %
(self.Name, araddr, arlen, arsize))
def monitorResp():
global respState, data0, data1, data2
resp_count = logs.peek('tb.resp_count')
if (resp_count == 0) and (respState == 'idle'):
veri.force('tb.resp_read', '0')
else:
if respState == 'idle':
veri.force('tb.resp_read', '1')
veri.force('tb.resp_addr', '0')
respState = '1'
elif respState == '1':
data0 = logs.peek('tb.resp_data')
veri.force('tb.resp_addr', '1')
respState = '2'
elif respState == '2':
data1 = logs.peek('tb.resp_data')
veri.force('tb.resp_addr', '2')
respState = '3'
elif respState == '3':
data2 = logs.peek('tb.resp_data')
respState = '4'
Msg = data0 | (data1 << 64) | (data2 << 128)
logs.log_info('resp fifo %x ' % (Msg))
(Cmd, Tags, Bytes, Addr, Data) = parseMsg(Msg)
logs.log_info(
'responce cmd=%s tags=%x bytes=%x addr=%08x data=%x' %
(cmdKind(Cmd), Tags, Bytes, Addr, Data))
veri.force('tb.resp_addr', '3')
elif respState == '4':
respState = 'idle'
veri.force('tb.resp_addr', '0')
def check_instance_against_module(Current, Instobj, modules):
Type = Instobj.Type
Son = modules[Type]
Conns = Instobj.conns.keys()
Conns.sort()
Exts = []
for Net in Son.nets:
(Dir, _) = Son.nets[Net]
if Dir not in ['wire', 'reg']:
Exts.append(Net)
Exts.sort()
Bads = 0
for A1 in Conns:
if A1 not in Exts:
log_error(
'check_instance_against_module connected pin=%s of instance=%s of module=%s not in definition of module %s'
% (A1, Instobj.Name, Current.Module, Type))
Bads += 1
if (Bads > 0):
for Ext in Exts:
log_info('ext: %s' % Ext)
for A2 in Exts:
if A2 not in Conns:
print 'check_instance_against_module external pin=%s of module %s not connected at instance=%s in module=%s' % (
A2, Type, Instobj.Name, Current.Module)
def negedge():
global cycles
cycles += 1
if cycles > 1000:
logs.log_info('finish')
veri.finish()
sys.exit()
def work(File,startTime,endTime):
global Time,linenum
while 1:
line=File.readline()
linenum +=1
if (linenum % 1000000)==0:
logs.log_info('line in=%d time=%s'%(linenum,Time))
if (len(line)==0):
return
wrds = string.split(line)
if (len(wrds)==0):
pass
elif (wrds[0]=='$dumpvars'):
pass
elif (wrds[0]=='$end'):
pass
elif (wrds[0][0]=='#'):
Time = int(wrds[0][1:])
elif (len(wrds)==2)and(wrds[0][0]=='b'):
Str = wrds[0][1:]
Code = wrds[1]
if Code in Codes:
Sig = Codes[wrds[1]]
use_value(Sig,Str,Time)
elif (len(wrds)==1):
Str = wrds[0][0]
Code = wrds[0][1:]
if (Code in Codes):
Sig = Codes[Code]
use_value(Sig,Str,Time)
def read_headers(File,mainPaths):
state='idle'
Path = []
Pathstr = ''
lnum=0
while 1:
line=File.readline()
lnum += 1
if (len(line)==0):
logs.log_error('ended in headers')
return
wrds = string.split(line)
if (len(wrds)==0):
pass
elif (wrds[0]=='$scope'):
Path.append(wrds[2])
Pathstr = string.join(Path,'.')
allPaths.append(Pathstr)
elif (wrds[0]=='$var')and(wrds[1] in ['reg','wire','integer']):
Wid = int(wrds[2])
Code = wrds[3]
Sig = wrds[4]
add_sig(Pathstr,Sig,Wid,Code,mainPaths)
elif (wrds[0]=='$upscope'):
Path.pop(-1)
Pathstr = string.join(Path,'.')
elif (wrds[0]=='$enddefinitions'):
logs.log_info('enddefs %d'%lnum)
return
elif (wrds[0][0]=='#'):
logs.log_info('enddefs %d'%lnum)
return
def makeWrite(self, Burst, Len, Address, Size=4, Wdatas=[]):
self.Queue.append((
'aw',
'force awvalid=1 awburst=%s awlen=%s awaddr=%s awsize=%s awid=%s' %
(Burst, Len - 1, Address, Size, self.Rid)))
self.Queue.append(
('aw',
'force awvalid=0 awburst=0 awlen=0 awaddr=0 awsize=0 awid=0'))
logs.log_info('makeWrite >>>>> %x size=%s' % (Address, Size))
self.Rid += 1
for ii in range(Len):
if len(Wdatas) == 0:
Wdata = '0x%08x%08x%08x%08x' % (self.Rid + 0x1000 * ii,
0x100 + self.Rid + 0x1000 * ii,
0x200 + self.Rid + 0x1000 * ii,
0x300 + self.Rid + 0x1000 * ii)
elif (type(Wdatas[0]) == types.StringType):
Wdata = Wdatas.pop(0)
else:
Wdata = hex(Wdatas.pop(0))
if ii == (Len - 1):
Wlast = 1
else:
Wlast = 0
Wstrb = (1 << (1 << Size)) - 1
self.Queue.append(
('w', 'force wvalid=1 wdata=%s wstrb=0x%x wlast=%d' %
(Wdata, Wstrb, Wlast)))
self.Queue.append(('w', 'force wvalid=0 wdata=0 wstrb=0 wlast=0'))
def action(self, Txt):
wrds = Txt.split()
Cmd = wrds[0]
if Cmd == 'send':
Str = ''
for Wrd in wrds[1:]:
if Wrd == '?':
Str += '????????'
else:
Abin = logs.binx(Wrd, 8)
Str += Abin
logs.log_info('SEND SPI %d %s' % (len(Str), Str))
self.send(Str, 1)
return
if Cmd == 'read':
if len(wrds) == 2:
self.read(wrds[1])
else:
self.read(wrds[1], wrds[2])
elif Cmd == 'write':
self.write(wrds[1], wrds[2])
elif Cmd == 'wait':
self.wait(wrds[1])
elif Cmd == 'waitNotBusy':
return
else:
logs.log_error('spiMaster action not recogninzed "%s"' % Txt)
def __init__(self,Path,Monitors,Name='optional'):
self.Path = Path
self.Name = Name
self.queue0=[]
self.seq0=[]
self.waiting0=0
self.wait_until0 = False
self.queue1=[]
self.seq1=[]
self.waiting1=0
self.wait_until1 = False
self.translations={}
self.renames={}
self.prefix = ''
self.markers={}
self.finishes=False
self.hexMode = False
self.Backs = []
if Monitors != -1:
Monitors.append(self)
self.Caller = False
logs.log_info('apbDriver ver 27.apr.2021')
self.noList = []
if not self.exists('pstrb'):
self.noList.append('pstrb')
logs.log_warning('NO PSTRB detected for apb master %s' % (self.Name))
def on_key_press(Chr, Ord, xy):
# if (Chr=='Q'): # Q key
# sys.exit()
if (Chr == 'h'):
logs.log_info(helpString.helpString)
else:
dbase.use_keystroke(Chr, Ord, xy)
def action(self, Txt):
if 'enable' in Txt:
self.Enable = True
return
if 'disable' in Txt:
self.Enable = False
return
if 'snapshot' in Txt:
counts.snapshot()
return
wrds = Txt.split()
if wrds[0] == []:
pass
elif wrds[0] == 'chance':
self.Chance = eval(wrds[1]) + 1
elif wrds[0] == 'masters':
self.Masters = []
for X in wrds[1:]:
self.Masters.append(eval(X))
elif wrds[0] == 'lens':
self.Lens = []
for X in wrds[1:]:
self.Lens.append(eval(X))
elif wrds[0] == 'address':
self.Addresses = []
for X in wrds[1:]:
self.Addresses.append(eval(X))
logs.log_info('ADDRESSES %s' % (list(map(hex, self.Addresses))))
else:
logs.log_error('ACTION unrecognized "%s" ' % Txt)
def report(self):
for RgfName in self.regfiles:
Rgf = self.regfiles[RgfName]
for RegName in Rgf.regs:
Reg = Rgf.regs[RegName]
X = Reg.generate()
logs.log_info('%s %s %x %x' % (RgfName, RegName, X, Reg.Addr))
def __init__(self, Path, Monitors, SEQUENCE='', AGENTS=[], Translates={}):
self.Path = Path
self.Name = 'main'
self.testFileName = '?'
logs.testFileName = '?'
if Monitors != -1:
Monitors.append(self)
self.Monitors = Monitors
self.Sequence = []
logs.log_info('INCLUDES STARTED')
self.workIncludes()
logs.log_info('INCLUDES DONE')
self.waiting = 0
self.Guardian = 0 # against wait too long.
self.waitNotBusy = False
self.agents = {}
self.agents['logs'] = logs
self.Translates = Translates
self.Translates['rnd'] = self.rnd
self.Translates['envir'] = self.envir
self.Translates['eflash'] = self.eflash
self.Translates['peek'] = self.seq_peek
for (Nickname, Object) in AGENTS:
self.agents[Nickname] = Object
Object.Caller = self
Object.SeqObj = self
self.searchPath = ['.']
self.Ptr = 0
self.Stack = []
self.Labels = {}
self.Subs = {}
self.Sons = []
self.Seed = 0
self.onFinishes = False
def runQueue():
global waiting
# if len(Queue)>0:
# logs.log_info('waiting=%d cmd0=%s len=%d '%(waiting,Queue[0],len(Queue)))
# else:
# logs.log_info('waiting=%d cmd0=0 len=%d '%(waiting,len(Queue)))
if (waiting > 0):
waiting -= 1
return
while Queue != []:
Cmd = Queue.pop(0)
if Cmd[0] == 'wait':
waiting = int(Cmd[1]) - 1
return
if Cmd[0] == 'finish':
logs.log_info('finishing on queue command')
sys.exit()
veri.finish()
return
if Cmd[0] == 'force':
veri.force('tb.' + Cmd[1], str(Cmd[2]))
# logs.log_info('forcing %s %s'%(Cmd[1],Cmd[2]))
else:
logs.log_error('bad queue directive "%s"' % str(Cmd))
def evalExpr(self, Wrds1):
self.Defs = {}
self.DEFS = []
Wrds = Wrds1[:]
for ind, Wrd in enumerate(Wrds):
if (str(Wrd)[0] in '_' + string.ascii_letters) and (Wrd not in [
'or', 'and', 'not'
]):
if Wrd in self.Translates:
self.Defs[Wrd] = self.Translates[Wrd]
Wrds[ind] = self.Translates[Wrd]
elif self.exists(Wrd):
Val = self.peek(Wrd)
self.Defs[Wrd] = Val
self.DEFS.append((Wrd, Val))
Wrds[ind] = Val
Txt = ' '.join(map(str, Wrds))
if Txt == '': return 0
try:
X = eval(Txt, self.Defs, self.Translates)
return X
except:
logs.log_error('evaluation of %s failed' % Txt, 0, True, True)
logs.log_info('TRANSLATES %s' % (str(self.Translates)))
logs.log_info('RDS %s' % (str(Wrds)))
return 0
def getQ(Pin, Obj, Mod, MakeReg=True):
if Pin not in Obj.conns: return ''
Q = Obj.conns[Pin]
logs.log_info('getQ %s=%s %s %s' % (Pin, Q, Obj.Name, Obj.Type))
if MakeReg:
if type(Q) is str:
if Q not in Mod.nets:
Mod.nets[Q] = 'reg', 0
elif 'output' in Mod.nets[Q]:
Mod.nets[Q] = 'output reg', 0
else:
Mod.nets[Q] = 'reg', 0
elif (Q[0] == 'subbit'):
Bus = Q[1]
Ind = eval(Q[2])
if Bus not in Mod.nets:
Mod.nets[Bus] = 'reg', (Ind, 0)
elif 'output' in Mod.nets[Bus]:
_, Wid = Mod.nets[Bus]
Wid = max(Wid[0], Ind), 0
Mod.nets[Bus] = 'output reg', Wid
else:
_, Wid = Mod.nets[Bus]
Wid = max(Wid[0], Ind), 0
Mod.nets[Bus] = 'reg', Wid
return Q
def sendrqueue(self):
if self.waitread > 0:
self.waitread -= 1
self.idleread()
return
if self.peek('rready') == 0:
self.idleread()
return
if self.rqueue == []:
self.idleread()
return
if self.rqueue[0] == 'pop':
self.rqueue.pop(0)
self.arqueue.pop(0)
self.idleread()
return
(rlast, rid, rdata) = self.rqueue.pop(0)
if rlast == 'wait':
self.waitread = rid
logs.log_info('axiSlave waitread %s' % rid)
self.idleread()
return
self.force('rvalid', 1)
self.force('rlast', rlast)
self.force('rid', rid)
self.force('rresp', 0)
self.force('rdata', '0x' + rdata)
def help_main(Env):
Types = {}
for Module in Env.Modules:
Mod = Env.Modules[Module]
logs.log_info('scan %s' % Module)
gatherInstances(Mod, Types)
reportInstances(Types)
def readQueue(self, ii, burst, arsize, addr, rid, rlast):
Incr = 1 << arsize
Mask = ~((1 << arsize) - 1)
if burst == 0:
Addr = addr
else:
Addr = ii * Incr + addr
Addr1 = Addr & Mask
if Addr1 != Addr:
logs.log_warning(
'axiSlave read address is not aligned size=%d addrin=%08x' %
(arsize, Addr))
rdata = ''
takenram = 0
for ii in range(16):
Add = Addr1 + ii
if Add in self.Ram:
AA = '%02x' % (self.Ram[Add])
takenram += 1
# logs.log_info('axiSlave addr in ram %x '%(Add))
else:
# AA = '%02x'%(0xff)
AA = '%02x' % (self.bytex)
self.bytex += 1
# logs.log_info('axiSlave addr not in ram %x '%(Add))
rdata = AA + rdata
self.rqueue.append((rlast, rid, rdata))
logs.log_info('axiSlave taken from ram %d bytes rdata=%s addr=%08x' %
(takenram, rdata, Addr))
def setupMain(Env):
params = logs.parse_args()
Env.systemverilog = '-sv' in params
Env.params = params
if (len(params.keys()) == 1):
if (params['fnames'] == []):
print_help()
logs.log_info('nothing given to do. exiting.')
return
Fnames = params['fnames']
logs.log_info('fnames: %s' % (str(Fnames)))
if ('-rundir' in params):
Env.rundir = params['-rundir'][0]
if not os.path.exists(Env.rundir):
os.mkdir(Env.rundir)
else:
Env.rundir = '.'
if ('-y' in params):
Env.SearchDirs.extend(params['-y'])
if ('-ext' in params):
Env.VerilogExtensions.extend(params['-ext'])
Env.GateLevelRead = ('-glv' in params)
Env.read_verilog_file = read_verilog_file
Env.read_gate_level_verilog_file = read_gate_level_verilog_file
Env.params = params
for Fname in Fnames:
if Env.GateLevelRead:
Env.read_gate_level_verilog_file(Fname, Env.rundir)
else:
Env.read_verilog_file(Fname, Env.rundir, Env)
logs.record_directory(Fname, Env.SearchDirs)
def cross_mos(Dict, Insts, Mod):
logs.log_info('cross_mos %s %s' % (Dict, Insts))
Mod.add_inst_conns('cross_mos', invent_inst('cross'),
[('i0', Dict['?I0']), ('i1', Dict['?I1']),
('q0', Dict['?Q0']), ('q1', Dict['?Q1'])])
for Inst in Insts:
Mod.insts.pop(Inst)
def elaborateSimpleAssigns(Mod):
Mod.prepareNetTable()
Ind = 0
dones = 0
failed = 0
while Ind < len(Mod.hard_assigns):
done = False
Dst, Src, _, _ = Mod.hard_assigns[Ind]
if (str(Dst) in Mod.netTable): #and (str(Src) in Mod.netTable):
if (str(Dst) in Mod.nets) and ((str(Src) in Mod.nets) or
(Src[0] in ['subbus', 'subbit'])):
Ldst = Mod.netTable[Dst]
for (Inst, Type, Pin) in Ldst:
# Lsrc = Mod.netTable[Src]
# if (len(Ldst)==1)and(len(Lsrc)==1):
# (Inst,Type,Pin) = Ldst[0]
Mod.insts[Inst].conns[Pin] = Src
Mod.hard_assigns.pop(Ind)
done = True
dones += 1
if not done:
Ind += 1
failed += 1
logs.log_info('elaborateSimpleAssigns did %d replacements and skipped %d' %
(dones, failed))
def Dlatch2(Dict, Insts, Mod):
logs.log_info('dlatch2 %s %s' % (Insts, Dict))
Dont = False
if Dict['?Ny'] == Dict['?N1']:
RB = Dict['?Ny']
Din = Dict['?Nz']
elif Dict['?Nz'] == Dict['?N1']:
RB = Dict['?Nz']
Din = Dict['?Ny']
elif Dict['?Ny'] == Dict['?N2']:
RB = Dict['?Ny']
Din = Dict['?Nz']
elif Dict['?Nz'] == Dict['?N2']:
RB = Dict['?Nz']
Din = Dict['?Ny']
else:
logs_error("Dlatch2 %s %s %s %s %s" %
(Dict['?Ny'], Dict['?Nz'], Dict['?N1'], Dict['?N2']))
Din = 'ERROR'
RB = 'ERROR'
Dont = True
if Dict['?Nx'] == Dict['?N20']:
Clk = Dict['?S0']
elif Dict['?Nx'] == Dict['?N21']:
Clk = Dict['?S1']
Mod.add_inst_conns('dlatch', invent_inst('dlatch'), [('qn', Dict['?QB']),
('q', Dict['?Q']),
('d', Din),
('rb', RB),
('clk', Clk)])
for Inst in Insts:
Mod.insts.pop(Inst)
def forcesAndPeeks(Mod, Fval):
Fval.write(STR0)
Index = 0
for Net in Mod.nets:
Dir, Wid = Mod.nets[Net]
if ('input' in Dir) or ('output' in Dir):
Wid1 = Wid
Wid = getWid(Net, Wid, Mod)
if Wid <= 64:
Str = STR1.replace('NET', Net)
Str = Str.replace('IND', str(Index))
Fval.write(Str)
RENAMES[Net] = Index
Index += 1
else:
logs.log_info('signal %s is not driven' % Net)
Fval.write(STR2)
for Net in Mod.nets:
Dir, Wid = Mod.nets[Net]
if ('input' in Dir) or ('output' in Dir):
Wid = getWid(Net, Wid, Mod)
Str = STR3.replace('NET', Net)
Str = Str.replace('IND', str(RENAMES[Net]))
if Wid <= 64:
Str = Str.replace('WID', str(Wid))
Fval.write(Str)
Fval.write(STR4)
def run_deep(Mod, Destinations, Distances, Actives):
Down = []
for Net in Actives:
if hashit(Net) in Mod.netTable:
Conns = Mod.netTable[hashit(Net)]
Base, Q = Distances[hashit(Net)]
Dist = 1 + Base
for Inst, Type, Pin in Conns:
if isInpPin(Pin, Type):
Opin = outPin(Type)
if Opin:
Osig = Mod.insts[Inst].conns[Opin]
if hashit(Osig) in Distances:
Now, From = Distances[hashit(Osig)]
else:
Now = 0
if hashit(Osig) in Destinations:
if Dist > Now: Distances[hashit(Osig)] = Dist, Q
elif Dist > Now:
Distances[hashit(Osig)] = Dist, Q
if Osig not in Down:
Down.append(Osig)
if (Down != []):
logs.log_info('Deeper %d' % len(Down))
run_deep(Mod, Destinations, Distances, Down)
