system.l2cache = L2Cache(size = '512kB', writeback_clean = True) system.l2cache.xbar = L2XBar() system.l1cache.mem_side = system.l2cache.xbar.slave system.l2cache.cpu_side = system.l2cache.xbar.master # make the L3 mostly exclusive, and correspondingly ensure that the L2 # writes back also clean lines to the L3 system.l3cache = L3Cache(size = '4MB', clusivity = 'mostly_excl') system.l3cache.xbar = L2XBar() system.l2cache.mem_side = system.l3cache.xbar.slave system.l3cache.cpu_side = system.l3cache.xbar.master system.l3cache.mem_side = system.membus.slave # connect the system port even if it is not used in this example system.system_port = system.membus.slave # every period, dump and reset all stats periodicStatDump(period) # run Forrest, run! root = Root(full_system = False, system = system) root.system.mem_mode = 'timing' m5.instantiate() m5.simulate(nxt_state * period) # print all we need to make sense of the stats output print("lat_mem_rd with %d iterations, ranges:" % iterations) for r in ranges: print(r)
system.l2cache = L2Cache(size='512kB', writeback_clean=True) system.l2cache.xbar = L2XBar() system.l1cache.mem_side = system.l2cache.xbar.slave system.l2cache.cpu_side = system.l2cache.xbar.master # make the L3 mostly exclusive, and correspondingly ensure that the L2 # writes back also clean lines to the L3 system.l3cache = L3Cache(size='4MB', clusivity='mostly_excl') system.l3cache.xbar = L2XBar() system.l2cache.mem_side = system.l3cache.xbar.slave system.l3cache.cpu_side = system.l3cache.xbar.master system.l3cache.mem_side = system.membus.slave # connect the system port even if it is not used in this example system.system_port = system.membus.slave # every period, dump and reset all stats periodicStatDump(period) # run Forrest, run! root = Root(full_system=False, system=system) root.system.mem_mode = 'timing' m5.instantiate() m5.simulate(nxt_state * period) # print all we need to make sense of the stats output print("lat_mem_rd with %d iterations, ranges:" % iterations) for r in ranges: print(r)
# Note that the interrupt controller is always present but only # in x86 does it have message ports that need to be connected system.cpu[i].createInterruptController() # Connect the cpu's cache ports to Ruby system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave if buildEnv['TARGET_ISA'] == 'x86': system.cpu[i].interrupts[0].pio = ruby_port.master system.cpu[i].interrupts[0].int_master = ruby_port.slave system.cpu[i].interrupts[0].int_slave = ruby_port.master system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave else: MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.membus.width = options.mem_bus_width system.membus.respwidth = options.mem_resp_width system.membus.clk_domain = system.cpu_clk_domain system.membus.frontend_latency = options.mem_front_lat system.membus.forward_latency = options.mem_forw_lat system.membus.response_latency = options.mem_resp_lat system.system_port = system.membus.slave CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) if options.stat_dump_period != 0: periodicStatDump(options.stat_dump_period) root = Root(full_system=False, system=system) Simulation.run(options, root, system, FutureClass)