def test_small():
path = full_path("small.v")
small = m.DeclareFromVerilogFile(path)[0]
for name in small.IO():
assert name in ["in", "out"]
for name in small.interface:
assert name in ["in", "out"]
for item in small.interface.items():
assert item in [("in", m.In(m.Bit)), ("out", m.Out(m.Bit))]
def test_small():
file_path = os.path.dirname(__file__)
file_name = os.path.join(file_path, "small.v")
small = m.DeclareFromVerilogFile(file_name)[0]
for name in small.IO():
assert name in ["in", "out"]
for name in small.interface:
assert name in ["in", "out"]
for item in small.interface.items():
assert item in [("in", m.In(m.Bit)), ("out", m.Out(m.Bit))]
def DefineTester(cgra_file, collateral_file, wrapped_name):
cgra_def = m.DeclareFromVerilogFile(cgra_file)[0]
with open(collateral_file, 'r') as f:
io_d = json.load(f)
ios = _flatten(
chain(_CGRA_SIGNAL_PORTS,
((mod, m.Array(int(c['width']), _s2b(c['mode'])))
for mod, c in io_d.items())))
class Tester(m.Circuit):
name = wrapped_name
IO = ios
@classmethod
def definition(io):
cgra = cgra_def()
for port in io.interface:
if port in io_d:
#port is a pin
direct = io_d[port]['mode']
for bit, pad in io_d[port]['bits'].items():
try:
#pad + '_' + direct is the 'de-tristated' name
m.wire(cgra.interface[pad + '_' + direct],
io.interface[port][int(bit)])
except KeyError as e:
Print(
'Looks like their is some sort of inconsistency between the cgra_info (or at least the collateral) and top.v'
)
raise e
else:
#port is a control signal
try:
m.wire(cgra.interface[port], io.interface[port])
except KeyError as e:
Print(
'Looks like _CGRA_SIGNAL_PORTS is no longer correct'
)
raise e
for port in cgra.interface:
if cgra.interface[port].value() is None and isinstance(
cgra.interface[port], m.BitIn):
m.wire(cgra.interface[port], m.GND)
return Tester
def __init__(self, filename):
underlying = magma.DeclareFromVerilogFile(filename)[0]
super().__init__(underlying)
m.wire(cam.DATA, process.DATA)
m.wire(cam.VALID, process.VALID)
# Rescaling image
rescale = Rescale()
m.wire(main.CLKIN, rescale.CLK)
m.wire(process.PXV, rescale.DATA)
m.wire(sclk, rescale.SCK)
m.wire(process.LOAD, rescale.LOAD)
# register on input
bitin = mantle.Register(1, has_ce=True)
bitin(m.array(rescale.O))
m.wire(process.LOAD, bitin.CE)
Convolution = m.DeclareFromVerilogFile('build/convolution.v',
module="Convolution")
conv = WrapInst(Convolution())
m.wire(~sclk, conv.CLK)
m.wire(bitin, conv.I0[0][0])
m.wire(weights, conv.I1)
m.wire(rescale.VALID, conv.WE)
# Wire up camera SPI bus
m.wire(sclk, main.J2_3)
m.wire(cam.EN, main.J2_4)
m.wire(cam.MOSI, main.J2_5)
# Wire up GPIOs for debugging
m.wire(cam.UART, main.J2_9)