def __init__(self, args):
type_map = {"clk": m.In(m.Clock),
"reset": m.In(m.AsyncReset)}
top_filename = args.top_filename
stub_filename = args.stub_filename
config_file = args.config_file
# detect the environment
if shutil.which("ncsim"):
self.use_ncsim = True
else:
self.use_ncsim = False
# if it's ncsim, rename copy it to .sv extension
if self.use_ncsim:
new_filename = os.path.splitext(stub_filename)[0] + ".sv"
shutil.copy2(stub_filename, new_filename)
stub_filename = new_filename
self.circuit = m.define_from_verilog_file(
stub_filename,
target_modules=["Interconnect"],
type_map=type_map
)[0]
with open(config_file) as f:
config = json.load(f)
bitstream_file = config["bitstream"]
# load the bitstream
self.bitstream = []
with open(bitstream_file) as f:
for line in f.readlines():
addr, value = line.strip().split(" ")
addr = int(addr, 16)
value = int(value, 16)
self.bitstream.append((addr, value))
self.input_filename = config["input_filename"]
self.output_filename = f"{bitstream_file}.out"
self.gold_filename = config["gold_filename"]
self.output_port_name = config["output_port_name"]
self.input_port_name = config["input_port_name"]
self.valid_port_name = config["valid_port_name"] \
if "valid_port_name" in config else ""
self.reset_port_name = config["reset_port_name"] \
if "reset_port_name" in config else ""
self.en_port_name = config["en_port_name"]\
if "en_port_name" in config else ""
self.top_filename = top_filename
self._input_size = 1
self._output_size = 1
self._loop_size = 0
self.pixel_size = 1
self.delay = config["delay"] if "delay" in config else 0
self._check_input(self.input_filename)
self._check_output(self.gold_filename)
def test_tester_verilog_wrapped(target, simulator):
ConfigReg, SimpleALU = m.define_from_verilog_file(
"tests/simple_alu.v",
type_map={"CLK": m.In(m.Clock)},
target_modules=["SimpleALU", "ConfigReg"])
with SimpleALU.open():
ConfigReg()
class circ(m.Circuit):
name = 'top'
io = m.IO(a=m.In(m.Bits[16]),
b=m.In(m.Bits[16]),
c=m.Out(m.Bits[16]),
config_data=m.In(m.Bits[2]),
config_en=m.In(m.Bit),
CLK=m.In(m.Clock))
simple_alu = SimpleALU()
simple_alu.a @= io.a
simple_alu.b @= io.b
io.c @= simple_alu.c
simple_alu.config_data @= io.config_data
simple_alu.config_en @= io.config_en
simple_alu.CLK @= io.CLK
tester = fault.Tester(circ, circ.CLK)
tester.verilator_include("SimpleALU")
tester.verilator_include("ConfigReg")
tester.circuit.CLK = 0
for i in range(0, 4):
tester.poke(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]), i)
tester.step(2)
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]), i)
signal = tester.peek(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]))
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.opcode",
m.Bits[2]), signal)
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]), i)
signal = tester.peek(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]))
tester.expect(
fault.WrappedVerilogInternalPort("SimpleALU_inst0.config_reg.Q",
m.Bits[2]), signal)
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target,
directory=_dir,
flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
def test_tap(width=5):
# declare circuit
dut = m.define_from_verilog_file(TOP / 'tests' / 'verilog' / 'dut.v')[0]
# instantiate tester
t = JTAGLowLevelDriver(dut, width=width, svf_file='out.svf')
# reset the driver
t.reset()
# read ID
id_val = t.read_id()
# run simulation
DW_tap_v = TOP / 'noupload' / 'DW_tap.v'
t.compile_and_run(
target='system-verilog',
simulator='iverilog',
ext_libs=[DW_tap_v]
)
# print ID
print('JTAG ID:')
print('{0:0{1}x}'.format(id_val.value, 8))
def test_addr_design(test_rand,
design,
starting_addr=0,
strides_0=15,
strides_1=13,
ranges_0=5,
ranges_1=6):
if test_rand:
max_value = 2**5
starting_addr = random.randint(0, max_value - 1)
strides_0 = random.randint(0, max_value - 1)
strides_1 = random.randint(0, max_value - 1)
ranges_0 = random.randint(0, max_value - 1)
ranges_1 = random.randint(0, max_value - 1)
print(starting_addr, strides_0, strides_1, ranges_0, ranges_1)
# set up addressor model
model_ag = AddrGenModel(2, 16)
config = {}
config["starting_addr"] = starting_addr
config["dimensionality"] = 2
config["strides_0"] = strides_0
config["strides_1"] = strides_1
config["ranges_0"] = ranges_0
config["ranges_1"] = ranges_1
model_ag.set_config(config)
# set up frail design with Verilog
frail_dir = pathlib.Path(__file__).parent.parent.absolute()
# get Magma circuit from Verilog
dut = m.define_from_verilog_file(f"{frail_dir}/verilog/{design}.v",
target_modules=[design],
type_map={"clk": m.In(m.Clock)})[0]
print(f"Imported as magma circuit: {dut}")
tester = fault.Tester(dut, dut.clk)
# no need to rst_n or clk_en yet
# config regs
if design in ("design_b", "op_design", "nested"):
tranges, tstrides = transform_strides_and_ranges(
[ranges_0, ranges_1], [strides_0, strides_1], 2)
tester.circuit.x_max = ranges_0 #tranges[0]
tester.circuit.x_stride = tstrides[0]
tester.circuit.y_max = ranges_1 #tranges[1]
tester.circuit.y_stride = tstrides[1]
# tester.circuit.config_68_74_op = tstrides[1]
# tester.circuit.config_125_131_op = tstrides[1]
tester.circuit.y_stride_op = tstrides[1]
tester.circuit.offset = starting_addr
# print("transformed:", tranges, tstrides)
elif design == "piecewise_addr_design":
tester.circuit.x_max = ranges_0
tester.circuit.x_stride_0 = strides_0
tester.circuit.x_stride_1 = strides_0
tester.circuit.y_max = ranges_1
tester.circuit.y_stride_0 = strides_1
tester.circuit.y_stride_1 = strides_1
tester.circuit.offset_0 = starting_addr
tester.circuit.offset_1 = starting_addr
tester.circuit.offset_2 = starting_addr
tester.circuit.offset_3 = starting_addr
tester.circuit.i0_piece = ranges_0
tester.circuit.i1_piece = ranges_1
else:
tester.circuit.x_max = ranges_0
tester.circuit.x_stride = strides_0
tester.circuit.y_max = ranges_1
tester.circuit.y_stride = strides_1
tester.circuit.offset = starting_addr
tester.circuit.step = 1
for i in range(min(1000, ranges_0 * ranges_1 - 1)):
# start with first addr on rising clk edge
tester.circuit.clk = 1
tester.step(2)
tester.eval()
model_ag.step()
tester.circuit.addr_out.expect(model_ag.get_address())
# print(model_ag.get_address())
with tempfile.TemporaryDirectory() as tempdir:
# tempdir = design
shutil.copy(f"{frail_dir}/verilog/{design}.v", tempdir)
tester.compile_and_run(target="verilator",
directory=tempdir,
skip_compile=True,
flags=["-Wno-fatal"])
def test_simple_alu_pd():
type_map = {"CLK": m.In(m.Clock)}
circ = m.define_from_verilog_file("tests/verilog/simple_alu_pd.sv",
type_map=type_map)[0]
tester = fault.PowerTester(circ, circ.CLK)
tester.add_power(circ.VDD_HIGH)
tester.add_ground(circ.VSS)
tester.add_tri(circ.VDD_HIGH_TOP_VIRTUAL)
tester.circuit.CLK = 0
# Enable the power switch
tester.circuit.config_addr = 0x00080000
tester.circuit.config_data = 0xFFFFFFF0
tester.circuit.config_en = 1
tester.step(2)
tester.circuit.config_en = 0
# rest of test...
a, b = BitVector.random(16), BitVector.random(16)
tester.circuit.a = a
tester.circuit.b = b
tester.circuit.c.expect(a + b)
# Disable the power switch
tester.circuit.config_addr = 0x00080000
tester.circuit.config_data = 0xFFFFFFF0
tester.circuit.config_en = 1
tester.step(2)
tester.circuit.config_en = 0
# Stall global signal should be on when tile is off
tester.circuit.stall_out.expect(1)
# reset signal should be on when tile is off
tester.circuit.reset.expect(1)
# Enable the power switch
tester.circuit.config_addr = 0x00080000
tester.circuit.config_data = 0xFFFFFFF0
tester.circuit.config_en = 1
tester.step(2)
tester.circuit.config_en = 0
# rest of test...
a, b = BitVector.random(16), BitVector.random(16)
tester.circuit.a = a
tester.circuit.b = b
tester.circuit.c.expect(a + b)
try:
tester.compile_and_run(target="system-verilog",
simulator="ncsim",
directory="tests/build",
skip_compile=True)
except AssertionError:
# Won't run because we don't have concrete DUT or ncsim, but we check
# that the output has the right types for the special ports
with open("tests/build/simple_alu_pd_tb.sv", "r") as f:
for line in f.read().splitlines():
if "VDD_HIGH_TOP_VIRTUAL;" in line:
assert line.lstrip().rstrip() == \
"tri VDD_HIGH_TOP_VIRTUAL;"
elif "VDD_HIGH;" in line:
assert line.lstrip().rstrip() == "supply1 VDD_HIGH;"
elif "VSS;" in line:
assert line.lstrip().rstrip() == "supply0 VSS;"
def __init__(self, args):
type_map = {"clk": m.In(m.Clock), "reset": m.In(m.AsyncReset)}
top_filename = args.top_filename
stub_filename = args.stub_filename
config_file = args.config_file
# detect the environment
if shutil.which("xrun"):
self.use_xcelium = True
else:
self.use_xcelium = False
# if it's xcelium, rename copy it to .sv extension
if self.use_xcelium:
new_filename = os.path.splitext(stub_filename)[0] + ".sv"
shutil.copy2(stub_filename, new_filename)
stub_filename = new_filename
self.circuit = m.define_from_verilog_file(stub_filename,
target_modules=[
"Interconnect"
],
type_map=type_map)[0]
with open(config_file) as f:
config = json.load(f)
bitstream_file = config["bitstream"]
# load the bitstream
self.bitstream = []
with open(bitstream_file) as f:
for line in f.readlines():
addr, value = line.strip().split(" ")
addr = int(addr, 16)
value = int(value, 16)
self.bitstream.append((addr, value))
# compute the config pipeline interval
max_y = 0
for addr, _ in self.bitstream:
y = addr & 0xFF
if y > max_y:
max_y = y
config_pipeline_interval = 8
self.y_interval = ((max_y - 1) // 8) + 1
self.input_filename = config["input_filename"]
self.output_filename = f"{bitstream_file}.out"
self.gold_filename = config["gold_filename"]
self.output_port_name = config["output_port_name"]
self.input_port_name = config["input_port_name"]
self.valid_port_name = config["valid_port_name"] \
if "valid_port_name" in config else ""
self.reset_port_name = config["reset_port_name"] \
if "reset_port_name" in config else ""
self.en_port_name = config["en_port_name"]\
if "en_port_name" in config else ""
self.top_filename = top_filename
self._input_size = 1
self._output_size = 1
self._loop_size = 0
self.pixel_size = 1
self.delay = config["delay"] if "delay" in config else 0
self._check_input(self.input_filename)
self._check_output(self.gold_filename)
# if total cycle set, need to compute delay
if config.get("total_cycle", 0) > 0:
total_cycle = config["total_cycle"]
self.delay += total_cycle - self._loop_size