def get_cost(self): if self.machine.target == machine.TargetType.SIMPLE: return cost.Cost(self.size * self.word_size) elif self.machine.target == machine.TargetType.ASIC: return cost.Cost(cacti.get_area(self.machine, self)) elif self.machine.target == machine.TargetType.FPGA: return xilinx.get_cost(self.machine, self) else: assert(False)
def get_cost(self): if self.depth == 1: return self.machine.get_zero_cost() elif self.machine.target == TargetType.SIMPLE: return cost.Cost(self.depth * self.word_size) elif self.machine.target == TargetType.ASIC: return cost.Cost(cacti.get_area(self.machine, self)) elif self.machine.target == TargetType.FPGA: return xilinx.get_cost(self.machine, self) else: assert(False)
def get_cost(self): if self.machine.target == machine.TargetType.SIMPLE: index_bits = util.log2(self.line_count - 1) word_size = self.get_word_size() line_words = (self.line_size + word_size - 1) // word_size ls_bits = util.log2(line_words - 1) tag_bits = max(self.machine.addr_bits - index_bits - ls_bits, 0) width = 1 + tag_bits if self.associativity > 1: if self.policy == CachePolicy.PLRU: width += 1 else: width += util.log2(self.associativity - 1) if self.write_back: width += 1 width *= self.associativity depth = self.line_count // self.associativity return cost.Cost(width * depth) if self.machine.target == machine.TargetType.ASIC: return cost.Cost(cacti.get_area(self.machine, self)) elif self.machine.target == machine.TargetType.FPGA: return xilinx.get_cost(self.machine, self)