def generate_transform(self, op, value, inverse, gen, source): name = gen.get_name(source, self) jname = join.find_join(self.bank, self).get_id() word_size = self.get_word_size() addr_width = gen.get_addr_width(word_size) word_width = word_size * 8 oname = gen.generate_next(self, self.get_next()) bname = gen.generate_next(self, self.bank) gen.declare_signals(name, self.get_word_size()) # Transform into the bank. gen.add_code(name + '_inst : entity work.' + op) gen.enter() gen.add_code('generic map (') gen.enter() gen.add_code('ADDR_WIDTH => ' + str(addr_width) + ',') gen.add_code('WORD_WIDTH => ' + str(word_width) + ',') gen.add_code('VALUE => ' + str(value)) gen.leave() gen.add_code(")") gen.add_code("port map (") gen.enter() gen.add_code("clk => clk,") gen.add_code("rst => rst,") gen.add_code("addr => " + name + "_addr,") gen.add_code("din => " + name + "_din,") gen.add_code("dout => " + name + "_dout,") gen.add_code("re => " + name + "_re,") gen.add_code("we => " + name + "_we,") gen.add_code("mask => " + name + "_mask,") gen.add_code("ready => " + name + "_ready,") gen.add_code("maddr => " + bname + "_addr,") gen.add_code("min => " + bname + "_dout,") gen.add_code("mout => " + bname + "_din,") gen.add_code("mre => " + bname + "_re,") gen.add_code("mwe => " + bname + "_we,") gen.add_code("mmask => " + bname + "_mask,") gen.add_code("mready => " + bname + "_ready") gen.leave() gen.add_code(");") gen.leave() # Transform out of the bank. gen.add_code(jname + '_inst : entity work.' + op) gen.enter() gen.add_code('generic map (') gen.enter() gen.add_code('ADDR_WIDTH => ' + str(addr_width) + ',') gen.add_code("WORD_WIDTH => " + str(word_width) + ",") gen.add_code("VALUE => " + str(inverse)) gen.leave() gen.add_code(")") gen.add_code("port map (") gen.enter() gen.add_code("clk => clk,") gen.add_code("rst => rst,") gen.add_code("addr => " + jname + "_addr,") gen.add_code("din => " + jname + "_din,") gen.add_code("dout => " + jname + "_dout,") gen.add_code("re => " + jname + "_re,") gen.add_code("we => " + jname + "_we,") gen.add_code("mask => " + jname + "_mask,") gen.add_code("ready => " + jname + "_ready,") gen.add_code("maddr => " + oname + "_addr,") gen.add_code("min => " + oname + "_dout,") gen.add_code("mout => " + oname + "_din,") gen.add_code("mre => " + oname + "_re,") gen.add_code("mwe => " + oname + "_we,") gen.add_code("mmask => " + oname + "_mask,") gen.add_code("mready => " + oname + "_ready") gen.leave() gen.add_code(");") gen.leave() return name
def generate(self, gen, source): oname = gen.generate_next(self, self.get_next()) b0name = gen.generate_next(self, self.bank0) b1name = gen.generate_next(self, self.bank1) name = gen.get_name(source, self) j0name = join.find_join(self.bank0, self).get_id() j1name = join.find_join(self.bank1, self).get_id() word_size = self.get_word_size() word_width = word_size * 8 addr_width = gen.get_addr_width(word_size) word_offset = self.offset // word_size offset_bits = [] for i in reversed(xrange(0, addr_width)): if word_offset & (1 << i): offset_bits.append('1') else: offset_bits.append('0') offset_str = ''.join(offset_bits) gen.add_code(name + '_combine : entity work.combine') gen.enter() gen.add_code('generic map (') gen.enter() gen.add_code('ADDR_WIDTH => ' + str(addr_width) + ',') gen.add_code('WORD_WIDTH => ' + str(word_width) + ',') gen.add_code('OFFSET => "' + offset_str + '"') gen.leave() gen.add_code(')') gen.add_code('port map (') gen.enter() gen.add_code("clk => clk,") gen.add_code("rst => rst,") gen.add_code("addr0 => " + j0name + "_addr,") gen.add_code("din0 => " + j0name + "_din,") gen.add_code("dout0 => " + j0name + "_dout,") gen.add_code("re0 => " + j0name + "_re,") gen.add_code("we0 => " + j0name + "_we,") gen.add_code("mask0 => " + j0name + "_mask,") gen.add_code("ready0 => " + j0name + "_ready,") gen.add_code("addr1 => " + j1name + "_addr,") gen.add_code("din1 => " + j1name + "_din,") gen.add_code("dout1 => " + j1name + "_dout,") gen.add_code("re1 => " + j1name + "_re,") gen.add_code("we1 => " + j1name + "_we,") gen.add_code("mask1 => " + j1name + "_mask,") gen.add_code("ready1 => " + j1name + "_ready,") gen.add_code("maddr => " + oname + "_addr,") gen.add_code("mout => " + oname + "_din,") gen.add_code("min => " + oname + "_dout,") gen.add_code("mre => " + oname + "_re,") gen.add_code("mwe => " + oname + "_we,") gen.add_code("mmask => " + oname + "_mask,") gen.add_code("mready => " + oname + "_ready") gen.leave() gen.add_code(");") gen.leave() gen.declare_signals(name, word_size) gen.add_code(name + '_sp : entity work.split') gen.enter() gen.add_code('generic map (') gen.enter() gen.add_code('ADDR_WIDTH => ' + str(addr_width) + ',') gen.add_code("WORD_WIDTH => " + str(word_width) + ",") gen.add_code('OFFSET => "' + offset_str + '"') gen.leave() gen.add_code(")") gen.add_code("port map (") gen.add_code("clk => clk,") gen.add_code("rst => rst,") gen.add_code("addr => " + name + "_addr,") gen.add_code("din => " + name + "_din,") gen.add_code("dout => " + name + "_dout,") gen.add_code("re => " + name + "_re,") gen.add_code("we => " + name + "_we,") gen.add_code("mask => " + name + "_mask,") gen.add_code("ready => " + name + "_ready,") gen.add_code("maddr0 => " + b0name + "_addr,") gen.add_code("mout0 => " + b0name + "_din,") gen.add_code("min0 => " + b0name + "_dout,") gen.add_code("mre0 => " + b0name + "_re,") gen.add_code("mwe0 => " + b0name + "_we,") gen.add_code("mmask0 => " + b0name + "_mask,") gen.add_code("mready0 => " + b0name + "_ready,") gen.add_code("maddr1 => " + b1name + "_addr,") gen.add_code("mout1 => " + b1name + "_din,") gen.add_code("min1 => " + b1name + "_dout,") gen.add_code("mre1 => " + b1name + "_re,") gen.add_code("mwe1 => " + b1name + "_we,") gen.add_code("mmask1 => " + b1name + "_mask,") gen.add_code("mready1 => " + b1name + "_ready") gen.add_code(");") gen.leave() return name