def generate(self, gen, source):
name = source.get_id() + self.get_id()
word_size = self.get_word_size()
oname = gen.generate_next(self, self.get_next())
addr_width = gen.get_addr_width(word_size)
word_width = word_size * 8
line_size_bits = util.log2(8 * self.line_size // word_width - 1)
line_count_bits = \
util.log2(self.line_count // self.associativity - 1)
assoc_bits = util.log2(self.associativity - 1)
gen.declare_signals(name, self.get_word_size())
gen.add_code(name + '_inst : entity work.cache')
gen.enter()
gen.add_code('generic map (')
gen.enter()
gen.add_code('ADDR_WIDTH => ' + str(addr_width) + ',')
gen.add_code('WORD_WIDTH => ' + str(word_width) + ',')
gen.add_code('LINE_SIZE_BITS => ' + str(line_size_bits) + ',')
gen.add_code('LINE_COUNT_BITS => ' + str(line_count_bits) + ',')
gen.add_code('ASSOC_BITS => ' + str(assoc_bits) + ',')
replacement = -1
if self.policy == CachePolicy.LRU:
replacement = 0
elif self.policy == CachePolicy.MRU:
replacement = 1
elif self.policy == CachePolicy.FIFO:
replacement = 2
elif self.policy == CachePolicy.PLRU:
replacement = 3
assert(replacement >= 0)
gen.add_code('REPLACEMENT => ' + str(replacement) + ',')
if self.write_back:
gen.add_code('WRITE_POLICY => 0')
else:
gen.add_code('WRITE_POLICY => 1')
gen.leave()
gen.add_code(')')
gen.add_code('port map (')
gen.enter()
gen.add_code('clk => clk,')
gen.add_code('rst => rst,')
gen.add_code('addr => ' + name + '_addr,')
gen.add_code('din => ' + name + '_din,')
gen.add_code('dout => ' + name + '_dout,')
gen.add_code('re => ' + name + '_re,')
gen.add_code('we => ' + name + '_we,')
gen.add_code('mask => ' + name + '_mask,')
gen.add_code('ready => ' + name + '_ready,')
gen.add_code('maddr => ' + oname + '_addr,')
gen.add_code('min => ' + oname + '_dout,')
gen.add_code('mout => ' + oname + '_din,')
gen.add_code('mre => ' + oname + '_re,')
gen.add_code('mwe => ' + oname + '_we,')
gen.add_code('mmask => ' + oname + '_mask,')
gen.add_code('mready => ' + oname + '_ready')
gen.leave()
gen.add_code(');')
gen.leave()
return name
def get_cost(self):
if self.machine.target == machine.TargetType.SIMPLE:
index_bits = util.log2(self.line_count - 1)
word_size = self.get_word_size()
line_words = (self.line_size + word_size - 1) // word_size
ls_bits = util.log2(line_words - 1)
tag_bits = max(self.machine.addr_bits - index_bits - ls_bits, 0)
width = 1 + tag_bits
if self.associativity > 1:
if self.policy == CachePolicy.PLRU:
width += 1
else:
width += util.log2(self.associativity - 1)
if self.write_back:
width += 1
width *= self.associativity
depth = self.line_count // self.associativity
return cost.Cost(width * depth)
if self.machine.target == machine.TargetType.ASIC:
return cost.Cost(cacti.get_area(self.machine, self))
elif self.machine.target == machine.TargetType.FPGA:
return xilinx.get_cost(self.machine, self)
def generate(self, gen, source):
name = gen.get_name(source, self)
word_size = self.get_word_size()
word_width = word_size * 8
addr_width = gen.get_addr_width(word_size)
oname = gen.generate_next(self, self.get_next())
size_bits = util.log2(self.size // word_size) - 1
gen.declare_signals(name, word_size)
gen.add_code(name + '_inst : entity work.spm')
gen.enter()
gen.add_code('generic map (')
gen.enter()
gen.add_code('ADDR_WIDTH => ' + str(addr_width) + ',')
gen.add_code('WORD_WIDTH => ' + str(word_width) + ',')
gen.add_code('SIZE_BITS => ' + str(size_bits))
gen.leave()
gen.add_code(")")
gen.add_code("port map (")
gen.enter()
gen.add_code("clk => clk,")
gen.add_code("rst => rst,")
gen.add_code("addr => " + name + "_addr,")
gen.add_code("din => " + name + "_din,")
gen.add_code("dout => " + name + "_dout,")
gen.add_code("re => " + name + "_re,")
gen.add_code("we => " + name + "_we,")
gen.add_code("mask => " + name + "_mask,")
gen.add_code("ready => " + name + "_ready,")
gen.add_code("maddr => " + oname + "_addr,")
gen.add_code("min => " + oname + "_dout,")
gen.add_code("mout => " + oname + "_din,")
gen.add_code("mre => " + oname + "_re,")
gen.add_code("mwe => " + oname + "_we,")
gen.add_code("mmask => " + oname + "_mask,")
gen.add_code("mready => " + oname + "_ready")
gen.leave()
gen.add_code(");")
gen.leave()
return name
def test_log2(self):
self.assertEqual(util.log2(0), 0)
self.assertEqual(util.log2(5), 3)
self.assertEqual(util.log2(7), 3)
self.assertEqual(util.log2(8), 4)
