def __init__(self):
self.sb_hfosc_routing = HfoscRouting() # Internal oscillator routing.
LatticePlatform.__init__(self,
"ice40-up5k-sg48",
_io,
_connectors,
toolchain="icestorm")
def __init__(self):
# LatticePlatform.__init__(self, "lfe5u-45f-8bg381i", _io, _connectors, toolchain="trellis")
LatticePlatform.__init__(self,
"LFE5U-45F-8BG381C",
_io,
_connectors,
toolchain="diamond")
self.add_platform_command(
"""DEFINE PORT GROUP "ETH_TX" "eth_tx_data[3]"
"eth_tx_data[2]"
"eth_tx_data[1]"
"eth_tx_data[0]"
"eth_tx_ctl" ;""")
self.add_platform_command(
"""DEFINE PORT GROUP "ETH_RX" "eth_rx_data[3]"
"eth_rx_data[2]"
"eth_rx_data[1]"
"eth_rx_data[0]"
"eth_rx_ctl" ;""")
#self.add_platform_command("""CLOCK_TO_OUT GROUP "ETH_TX" -3 ns MIN -2.2 ns CLKNET "main_ethernetsoc_clk_0" CLKOUT PORT "eth_clocks_tx";""")
#self.add_platform_command("""INPUT_SETUP GROUP "ETH_RX" 1.2 ns HOLD 0.4 ns CLKPORT "eth_clocks_rx" ;""")
#self.add_platform_command("""FREQUENCY NET "clk_in_c" 125.000000 MHz ;""")
self.add_platform_command(
"""FREQUENCY NET "clk_in_c" 125.000000 MHz ;""")
self.add_platform_command(
"""FREQUENCY NET "eth_tx_clk" 125.000000 MHz ; """)
def __init__(self):
self.osch_clk_period = 1000.0 / 15.65
self.osch_routing = OschRouting() # Internal oscillator routing.
# Routed during self.do_finalize().
LatticePlatform.__init__(self,
"LCMXO2-1200HC-4SG32C",
_io,
_connectors,
toolchain="diamond")
def __init__(self, *args, **kwargs):
LatticePlatform.__init__(self,
self.device,
_io,
_connectors,
toolchain='trellis',
*args,
**kwargs)
self.add_period_constraint(self.default_clk_name,
self.default_clk_period)
def __init__(self, revision=None, toolchain="icestorm"):
self.revision = revision
if revision == "evt":
LatticePlatform.__init__(self, "ice40-up5k-sg48", _io_evt, _connectors, toolchain="icestorm")
elif revision == "dvt":
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io_dvt, _connectors, toolchain="icestorm")
elif revision == "pvt":
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io_pvt, _connectors, toolchain="icestorm")
elif revision == "hacker":
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io_hacker, _connectors, toolchain="icestorm")
else:
raise ValueError("Unrecognized reivsion: {}. Known values: evt, dvt, pvt, hacker".format(revision))
# All Fomu use 48MHz base clock.
self.clk_freq = 48000000
def __init__(self):
LatticePlatform.__init__(self,
"ice40-hx8k-ct256",
_io,
_connectors,
toolchain="icestorm")
def __init__(self):
LatticePlatform.__init__(self, "ice40-hx8k-ct256", _io,
toolchain="icestorm")
def __init__(self):
LatticePlatform.__init__(self, "ice40-1k-tq144", _io, _connectors,
toolchain="icestorm")
def __init__(self):
LatticePlatform.__init__(self, "ice40-8k-ct256", _io,
toolchain="icestorm")
def __init__(self):
LatticePlatform.__init__(self,
"ice40-hx1k-vq100",
_io,
_connectors,
toolchain="icestorm")
def __init__(self):
LatticePlatform.__init__(self,
"ice40-up5k-sg48",
_io,
_connectors,
toolchain="icestorm")
def __init__(self):
LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
def __init__(self):
LatticePlatform.__init__(self,
'ice40-up5k-sg48',
self._io,
self._connectors,
toolchain='icestorm')
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io, **kwargs)
def __init__(self):
LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
def __init__(self):
LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors,
toolchain="icestorm")
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io,
_connectors, **kwargs)
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io, **kwargs)
def __init__(self):
LatticePlatform.__init__(self, "ice40-1k-vq100", _io,
toolchain="icestorm")
def __init__(self):
LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors,
toolchain="icestorm")