def main(): parser = argparse.ArgumentParser( description="ARTIQ device binary builder for Kasli systems") parser.add_argument("--output-dir", default="artiq_sayma/rtm_gateware", help="output directory for generated " "source files and binaries") parser.add_argument("--no-compile-gateware", action="store_true", help="do not compile the gateware, only generate " "the CSR map") parser.add_argument("--csr-csv", default=None, help="store CSR map in CSV format into the " "specified file") args = parser.parse_args() platform = sayma_rtm.Platform() top = SaymaRTM(platform) os.makedirs(args.output_dir, exist_ok=True) with open(os.path.join(args.output_dir, "rtm_csr.csv"), "w") as f: f.write(get_csr_csv(top.csr_regions)) if not args.no_compile_gateware: platform.build(top, build_dir=args.output_dir, build_name="rtm")
def main(): build_dir = "artiq_sayma_rtm" platform = sayma_rtm.Platform() top = SaymaRTM(platform) os.makedirs(build_dir, exist_ok=True) with open(os.path.join(build_dir, "sayma_rtm_csr.csv"), "w") as f: f.write(get_csr_csv(top.csr_regions)) platform.build(top, build_dir=build_dir)
def __init__(self, **kwargs): platform = sayma_rtm.Platform(larger=True) SoCCore.__init__(self, platform, clk_freq=62.5e6, integrated_rom_size=0, integrated_sram_size=0, integrated_main_ram_size=256 * 1024, cpu_reset_address=self.mem_map["main_ram"], **kwargs) self.submodules.crg = CRG(platform)
def __init__(self, hw_rev=None, **kwargs): if hw_rev is None: hw_rev = "v2.0" self.hw_rev = hw_rev if hw_rev == "v1.0": platform = sayma_rtm.Platform(larger=True) elif hw_rev == "v2.0": platform = sayma_rtm2.Platform() else: raise ValueError SoCCore.__init__(self, platform, clk_freq=62.5e6, integrated_rom_size=0, integrated_sram_size=0, integrated_main_ram_size=256 * 1024, cpu_reset_address=self.mem_map["main_ram"], **kwargs) self.submodules.crg = CRG(platform, hw_rev)