Exemple #1
0
 def scan(self, ifargs, ifkwargs):
     self.banks = []
     self.srams = []
     for name, obj in xdir(self.source, True):
         if hasattr(obj, "get_csrs"):
             csrs = obj.get_csrs()
         else:
             csrs = []
         if hasattr(obj, "get_memories"):
             memories = obj.get_memories()
             for memory in memories:
                 mapaddr = self.address_map(name, memory)
                 sram_bus = csr.Interface(*ifargs, **ifkwargs)
                 mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
                 self.submodules += mmap
                 csrs += mmap.get_csrs()
                 self.srams.append((name, memory, mapaddr, mmap))
         if csrs:
             mapaddr = self.address_map(name, None)
             bank_bus = csr.Interface(*ifargs, **ifkwargs)
             rmap = Bank(csrs, mapaddr, bus=bank_bus)
             self.submodules += rmap
             self.banks.append((name, csrs, mapaddr, rmap))
Exemple #2
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    def __init__(self, description, address=0, bus=None):
        if bus is None:
            bus = csr.Interface()
        self.bus = bus

        ###

        if not description:
            return

        # Turn description into simple CSRs and claim ownership of compound CSR modules
        simple_csrs = []
        for c in description:
            if isinstance(c, CSR):
                simple_csrs.append(c)
            else:
                c.finalize(flen(self.bus.dat_w))
                simple_csrs += c.get_simple_csrs()
                self.submodules += c
        nbits = bits_for(len(simple_csrs) - 1)

        # Decode selection
        sel = Signal()
        self.comb += sel.eq(self.bus.adr[9:] == address)

        # Bus writes
        for i, c in enumerate(simple_csrs):
            self.comb += [
             c.r.eq(self.bus.dat_w[:c.size]),
             c.re.eq(sel & \
              self.bus.we & \
              (self.bus.adr[:nbits] == i))
            ]

        # Bus reads
        brcases = dict(
            (i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(simple_csrs))
        self.sync += [
            self.bus.dat_r.eq(0),
            If(sel, Case(self.bus.adr[:nbits], brcases))
        ]
Exemple #3
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	def __init__(self, bus_wishbone=None, bus_csr=None):
		if bus_wishbone is None:
			bus_wishbone = wishbone.Interface()
		self.wishbone = bus_wishbone
		if bus_csr is None:
			bus_csr = csr.Interface()
		self.csr = bus_csr

		###

		self.sync += [
			self.csr.we.eq(0),
			self.csr.dat_w.eq(self.wishbone.dat_w),
			self.csr.adr.eq(self.wishbone.adr),
			self.wishbone.dat_r.eq(self.csr.dat_r)
		]
		self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
			(1, [self.csr.we.eq(self.wishbone.we)]),
			(2, [self.wishbone.ack.eq(1)]),
			(3, [self.wishbone.ack.eq(0)])
		])
Exemple #4
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    def __init__(self,
                 platform,
                 clk_freq,
                 cpu_type="lm32",
                 cpu_reset_address=0x00000000,
                 integrated_rom_size=0,
                 integrated_sram_size=4096,
                 integrated_main_ram_size=0,
                 shadow_base=0x80000000,
                 with_csr=True,
                 csr_data_width=8,
                 csr_address_width=14,
                 with_uart=True,
                 uart_baudrate=115200,
                 with_identifier=True,
                 with_timer=True):
        self.platform = platform
        self.clk_freq = clk_freq

        self.cpu_type = cpu_type
        if integrated_rom_size:
            cpu_reset_address = 0
        self.cpu_reset_address = cpu_reset_address

        self.integrated_rom_size = integrated_rom_size
        self.integrated_sram_size = integrated_sram_size
        self.integrated_main_ram_size = integrated_main_ram_size

        self.with_uart = with_uart
        self.uart_baudrate = uart_baudrate

        self.with_identifier = with_identifier

        self.shadow_base = shadow_base

        self.with_csr = with_csr
        self.csr_data_width = csr_data_width
        self.csr_address_width = csr_address_width

        self._memory_regions = []  # list of (name, origin, length)
        self._csr_regions = [
        ]  # list of (name, origin, busword, csr_list/Memory)
        self._constants = []  # list of (name, value)

        self._wb_masters = []
        self._wb_slaves = []

        if cpu_type != "none":
            if cpu_type == "lm32":
                self.add_cpu_or_bridge(
                    lm32.LM32(platform, self.cpu_reset_address))
            elif cpu_type == "or1k":
                self.add_cpu_or_bridge(
                    mor1kx.MOR1KX(platform, self.cpu_reset_address))
            else:
                raise ValueError("Unsupported CPU type: {}".format(cpu_type))
            self.add_wb_master(self.cpu_or_bridge.ibus)
            self.add_wb_master(self.cpu_or_bridge.dbus)

            if integrated_rom_size:
                self.submodules.rom = wishbone.SRAM(integrated_rom_size,
                                                    read_only=True)
                self.register_rom(self.rom.bus, integrated_rom_size)

            if integrated_sram_size:
                self.submodules.sram = wishbone.SRAM(integrated_sram_size)
                self.register_mem("sram", self.mem_map["sram"], self.sram.bus,
                                  integrated_sram_size)

            # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
            if integrated_main_ram_size:
                self.submodules.main_ram = wishbone.SRAM(
                    integrated_main_ram_size)
                self.register_mem("main_ram", self.mem_map["main_ram"],
                                  self.main_ram.bus, integrated_main_ram_size)

        if with_csr:
            self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
                bus_csr=csr.Interface(csr_data_width, csr_address_width))
            self.register_mem("csr", self.mem_map["csr"],
                              self.wishbone2csr.wishbone)

            if with_uart:
                self.submodules.uart_phy = UARTPHY(platform.request("serial"),
                                                   clk_freq, uart_baudrate)
                self.submodules.uart = uart.UART(self.uart_phy)

            if with_identifier:
                platform_id = 0x554E if not hasattr(
                    platform, "identifier") else platform.identifier
                self.submodules.identifier = identifier.Identifier(
                    platform_id, int(clk_freq))

            if with_timer:
                self.submodules.timer0 = timer.Timer()
Exemple #5
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 def __init__(self):
     self.wishbone = wishbone.Interface()
     self.csr = csr.Interface()