def emit_verilog(instance, ns, clock_domains): r = instance.of + " " parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items)) if parameters: r += "#(\n" firstp = True for p in parameters: if not firstp: r += ",\n" firstp = False r += "\t." + p.name + "(" if isinstance(p.value, (int, bool)): r += verilog_printexpr(ns, p.value)[0] elif isinstance(p.value, float): r += str(p.value) elif isinstance(p.value, str): r += "\"" + p.value + "\"" else: raise TypeError r += ")" r += "\n) " r += ns.get_name(instance) if parameters: r += " " r += "(\n" firstp = True for p in instance.items: if isinstance(p, Instance._IO): name_inst = p.name name_design = verilog_printexpr(ns, p.expr)[0] elif isinstance(p, Instance.ClockPort): name_inst = p.name_inst name_design = ns.get_name(clock_domains[p.domain].clk) if p.invert: name_design = "~" + name_design elif isinstance(p, Instance.ResetPort): name_inst = p.name_inst name_design = ns.get_name(clock_domains[p.domain].rst) else: continue if not firstp: r += ",\n" firstp = False r += "\t." + name_inst + "(" + name_design + ")" if not firstp: r += "\n" r += ");\n\n" return r
def emit_verilog(instance, ns, add_data_file): r = instance.of + " " parameters = [ i for i in instance.items if isinstance(i, Instance.Parameter) ] if parameters: r += "#(\n" firstp = True for p in parameters: if not firstp: r += ",\n" firstp = False r += "\t." + p.name + "(" if isinstance(p.value, Constant): r += verilog_printexpr(ns, p.value)[0] elif isinstance(p.value, float): r += str(p.value) elif isinstance(p.value, Instance.PreformattedParam): r += p.value elif isinstance(p.value, str): r += "\"{}\"".format(p.value) else: raise TypeError r += ")" r += "\n) " r += ns.get_name(instance) if parameters: r += " " r += "(\n" firstp = True for p in instance.items: if isinstance(p, Instance._IO): name_inst = p.name name_design = verilog_printexpr(ns, p.expr)[0] if not firstp: r += ",\n" firstp = False r += "\t." + name_inst + "(" + name_design + ")" if not firstp: r += "\n" if instance.synthesis_directive is not None: synthesis_directive = "/* synthesis {} */".format( instance.synthesis_directive) r += ")" + synthesis_directive + ";\n\n" else: r += ");\n\n" return r
def emit_verilog(instance, ns, add_data_file): r = instance.of + " " parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items)) if parameters: r += "#(\n" firstp = True for p in parameters: if not firstp: r += ",\n" firstp = False r += "\t." + p.name + "(" if isinstance(p.value, Constant): r += verilog_printexpr(ns, p.value)[0] elif isinstance(p.value, float): r += str(p.value) elif isinstance(p.value, Instance.PreformattedParam): r += p.value elif isinstance(p.value, str): r += "\"" + p.value + "\"" else: raise TypeError r += ")" r += "\n) " r += ns.get_name(instance) if parameters: r += " " r += "(\n" firstp = True for p in instance.items: if isinstance(p, Instance._IO): name_inst = p.name name_design = verilog_printexpr(ns, p.expr)[0] if not firstp: r += ",\n" firstp = False r += "\t." + name_inst + "(" + name_design + ")" if not firstp: r += "\n" if instance.synthesis_directive is not None: synthesis_directive = "/* synthesis {} */".format(instance.synthesis_directive) r += ")" + synthesis_directive + ";\n\n" else: r += ");\n\n" return r
def emit_verilog(instance, ns): r = instance.of + " " parameters = list( filter(lambda i: isinstance(i, Instance.Parameter), instance.items)) if parameters: r += "#(\n" firstp = True for p in parameters: if not firstp: r += ",\n" firstp = False r += "\t." + p.name + "(" if isinstance(p.value, (int, bool)): r += verilog_printexpr(ns, p.value)[0] elif isinstance(p.value, float): r += str(p.value) elif isinstance(p.value, Instance.PreformattedParam): r += p.value elif isinstance(p.value, str): r += "\"" + p.value + "\"" else: raise TypeError r += ")" r += "\n) " r += ns.get_name(instance) if parameters: r += " " r += "(\n" firstp = True for p in instance.items: if isinstance(p, Instance._IO): name_inst = p.name name_design = verilog_printexpr(ns, p.expr)[0] if not firstp: r += ",\n" firstp = False r += "\t." + name_inst + "(" + name_design + ")" if not firstp: r += "\n" r += ");\n\n" return r
def emit_verilog(instance, ns): r = instance.of + " " parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items)) if parameters: r += "#(\n" firstp = True for p in parameters: if not firstp: r += ",\n" firstp = False r += "\t." + p.name + "(" if isinstance(p.value, (int, bool)): r += verilog_printexpr(ns, p.value)[0] elif isinstance(p.value, float): r += str(p.value) elif isinstance(p.value, Instance.PreformattedParam): r += p.value elif isinstance(p.value, str): r += "\"" + p.value + "\"" else: raise TypeError r += ")" r += "\n) " r += ns.get_name(instance) if parameters: r += " " r += "(\n" firstp = True for p in instance.items: if isinstance(p, Instance._IO): name_inst = p.name name_design = verilog_printexpr(ns, p.expr)[0] if not firstp: r += ",\n" firstp = False r += "\t." + name_inst + "(" + name_design + ")" if not firstp: r += "\n" r += ");\n\n" return r
def pe(e): return verilog_printexpr(ns, e)[0]
def gn(e): if isinstance(e, Memory): return ns.get_name(e) else: return verilog_printexpr(ns, e)[0]
def _get_name(e): if isinstance(e, Memory): return namespace.get_name(e) else: return verilog_printexpr(namespace, e)[0]