def __init__(self, width_or_layout, depth):
_FIFOInterface.__init__(self, width_or_layout, depth)
###
depth_bits = log2_int(depth, True)
produce = RenameClockDomains(GrayCounter(depth_bits + 1), "write")
consume = RenameClockDomains(GrayCounter(depth_bits + 1), "read")
self.submodules += produce, consume
self.comb += [
produce.ce.eq(self.writable & self.we),
consume.ce.eq(self.readable & self.re)
]
produce_rdomain = Signal(depth_bits + 1)
self.specials += [
NoRetiming(produce.q),
MultiReg(produce.q, produce_rdomain, "read")
]
consume_wdomain = Signal(depth_bits + 1)
self.specials += [
NoRetiming(consume.q),
MultiReg(consume.q, consume_wdomain, "write")
]
if depth_bits == 1:
self.comb += self.writable.eq(
(produce.q[-1] == consume_wdomain[-1])
| (produce.q[-2] == consume_wdomain[-2]))
else:
self.comb += [
self.writable.eq((produce.q[-1] == consume_wdomain[-1])
| (produce.q[-2] == consume_wdomain[-2])
| (produce.q[:-2] != consume_wdomain[:-2]))
]
self.comb += self.readable.eq(consume.q != produce_rdomain)
storage = Memory(self.width, depth)
self.specials += storage
wrport = storage.get_port(write_capable=True, clock_domain="write")
self.specials += wrport
self.comb += [
wrport.adr.eq(produce.q_binary[:-1]),
wrport.dat_w.eq(self.din_bits),
wrport.we.eq(produce.ce)
]
rdport = storage.get_port(clock_domain="read")
self.specials += rdport
self.comb += [
rdport.adr.eq(consume.q_next_binary[:-1]),
self.dout_bits.eq(rdport.dat_r)
]
def __init__(self, width, depth):
super().__init__(width, depth)
###
depth_bits = log2_int(depth, True)
produce = ClockDomainsRenamer("write")(GrayCounter(depth_bits + 1))
consume = ClockDomainsRenamer("read")(GrayCounter(depth_bits + 1))
self.submodules += produce, consume
self.comb += [
produce.ce.eq(self.writable & self.we),
consume.ce.eq(self.readable & self.re)
]
produce_rdomain = Signal(depth_bits + 1)
produce.q.attr.add("no_retiming")
self.specials += MultiReg(produce.q, produce_rdomain, "read")
consume_wdomain = Signal(depth_bits + 1)
consume.q.attr.add("no_retiming")
self.specials += MultiReg(consume.q, consume_wdomain, "write")
if depth_bits == 1:
self.comb += self.writable.eq(
(produce.q[-1] == consume_wdomain[-1]) |
(produce.q[-2] == consume_wdomain[-2]))
else:
self.comb += [
self.writable.eq(
(produce.q[-1] == consume_wdomain[-1]) |
(produce.q[-2] == consume_wdomain[-2]) |
(produce.q[:-2] != consume_wdomain[:-2]))
]
self.comb += self.readable.eq(consume.q != produce_rdomain)
storage = Memory(self.width, depth)
self.specials += storage
wrport = storage.get_port(write_capable=True, clock_domain="write")
self.specials += wrport
self.comb += [
wrport.adr.eq(produce.q_binary[:-1]),
wrport.dat_w.eq(self.din),
wrport.we.eq(produce.ce)
]
rdport = storage.get_port(clock_domain="read")
self.specials += rdport
self.comb += [
rdport.adr.eq(consume.q_next_binary[:-1]),
self.dout.eq(rdport.dat_r)
]
def __init__(self, period, width=6, clk=None):
self.clk = Signal() if clk is None else clk
self.value = CSRStatus(32)
# # #
self.clock_domains.cd_fmeter = ClockDomain(reset_less=True)
self.comb += self.cd_fmeter.clk.eq(self.clk)
# Period generation
period_done = Signal()
period_counter = Signal(32)
self.comb += period_done.eq(period_counter == period)
self.sync += \
If(period_done,
period_counter.eq(0),
).Else(
period_counter.eq(period_counter + 1)
)
# Frequency measurement
event_counter = ClockDomainsRenamer("fmeter")(GrayCounter(width))
gray_decoder = GrayDecoder(width)
sampler = _Sampler(width)
self.submodules += event_counter, gray_decoder, sampler
self.specials += MultiReg(event_counter.q, gray_decoder.i)
self.comb += [
event_counter.ce.eq(1),
sampler.latch.eq(period_done),
sampler.i.eq(gray_decoder.o),
self.value.status.eq(sampler.o)
]
def __init__(self, link_layer, rx_clock_domain):
self.aux_word_cnt = CSRStatus(64)
self.aux_zword_cnt = CSRStatus(64)
self.rt_word_cnt = CSRStatus(64)
self.rt_zword_cnt = CSRStatus(64)
self.update_link_stats = CSR()
# # #
aux_word = Signal()
aux_zword = Signal()
rt_word = Signal()
rt_zword = Signal()
sync = getattr(self.sync, rx_clock_domain)
sync += [
aux_word.eq(link_layer.rx_aux_frame_perm),
aux_zword.eq(link_layer.rx_aux_frame_perm
& (link_layer.rx_aux_data == 0)),
rt_word.eq(link_layer.rx_rt_frame_perm),
rt_zword.eq(link_layer.rx_rt_frame_perm
& (link_layer.rx_aux_data == 0))
]
for trigger, csr in [(aux_word, self.aux_word_cnt),
(aux_zword, self.aux_zword_cnt),
(rt_word, self.rt_word_cnt),
(rt_zword, self.rt_zword_cnt)]:
counter = ClockDomainsRenamer(rx_clock_domain)(GrayCounter(64))
decoder = GrayDecoder(64)
self.submodules += counter, decoder
counter.q.attr.add("no_retiming")
self.specials += MultiReg(counter.q, decoder.i)
self.comb += counter.ce.eq(trigger)
self.sync += If(self.update_link_stats.re,
csr.status.eq(decoder.o))
def __init__(self,
measure_clock,
measure_period,
measure_width=6,
counter_width=32):
self.value = CSRStatus(counter_width)
# # #
# create measure clock domain
self.clock_domains.cd_measure = ClockDomain(reset_less=True)
self.comb += self.cd_measure.clk.eq(measure_clock)
# mesure period
period_done = Signal()
period_counter = Signal(counter_width)
self.comb += period_done.eq(period_counter == measure_period)
self.sync += \
If(period_done,
period_counter.eq(0),
).Else(
period_counter.eq(period_counter + 1)
)
# measurement
event_counter = ClockDomainsRenamer("measure")(
GrayCounter(measure_width))
gray_decoder = GrayDecoder(measure_width)
sampler = Sampler(measure_width, counter_width)
self.submodules += event_counter, gray_decoder, sampler
self.specials += MultiReg(event_counter.q, gray_decoder.i)
self.comb += [
event_counter.ce.eq(1),
sampler.latch.eq(period_done),
sampler.i.eq(gray_decoder.o),
self.value.status.eq(sampler.value)
]
from random import Random
from migen import * # noqa
from migen.genlib.cdc import GrayCounter
def tb(dut):
prng = Random(7345)
for i in range(35):
print("{0:0{1}b} CE={2} bin={3}".format(
(yield dut.q), len(dut.q), (yield dut.ce), (yield dut.q_binary)))
yield dut.ce.eq(prng.getrandbits(1))
yield
if __name__ == "__main__":
dut = GrayCounter(3)
run_simulation(dut, tb(dut), vcd_name="graycounter.vcd")
def __init__(self, width=3): self.width = width self.submodules.gc = GrayCounter(self.width) self.prng = Random(7345)
def __init__(self, platform):
sys_clock_pads = platform.request("clk156")
self.clock_domains.cd_sys = ClockDomain(reset_less=True)
self.specials += Instance("IBUFGDS",
i_I=sys_clock_pads.p,
i_IB=sys_clock_pads.n,
o_O=self.cd_sys.clk)
sys_clk_freq = 156000000
self.comb += platform.request("sfp_tx_disable_n").eq(1)
gtx = GTXReceiver(clock_pads=platform.request("sgmii_clock"),
rx_pads=platform.request("sfp_rx"),
sys_clk_freq=sys_clk_freq)
self.submodules += gtx
# PRBS checker
checker = ClockDomainsRenamer("rx_clean")(CEInserter()(
PRBSChecker(16)))
self.submodules += checker
self.sync.rx += [
checker.ce.eq(~gtx.decoders[0].k),
checker.i[:8].eq(gtx.decoders[0].d),
checker.i[8:].eq(gtx.decoders[1].d)
]
error_accumulator = ClockDomainsRenamer("rx_clean")(GrayCounter(32))
self.submodules += error_accumulator
error_bits = [checker.errors[i] for i in range(len(checker.errors))]
self.comb += error_accumulator.ce.eq(reduce(or_, error_bits))
error_decoder = GrayDecoder(32)
self.submodules += error_decoder
self.specials += [
NoRetiming(error_accumulator.q),
MultiReg(error_accumulator.q, error_decoder.i)
]
# Wishbone target - I2C
i2c_master = I2CMaster(platform.request("i2c"))
self.submodules += i2c_master
# Wishbone target - PRBS error count
checker_wb = wishbone.Interface()
self.sync += [
checker_wb.dat_r.eq(error_decoder.o),
checker_wb.ack.eq(0),
If(checker_wb.cyc & checker_wb.stb & ~checker_wb.ack,
checker_wb.ack.eq(1))
]
# Wishbone master - Sequencer
sequencer = Sequencer(get_i2c_program(sys_clk_freq))
self.submodules += sequencer
# Wishbone master - UART bridge
uart_phy = RS232PHY(platform.request("serial"), sys_clk_freq, 115200)
bridge = WishboneStreamingBridge(uart_phy, sys_clk_freq)
self.submodules += uart_phy, bridge
# Wishbone interconnect
interconnect = wishbone.InterconnectShared(
[sequencer.bus, bridge.wishbone],
[(lambda a: a[4] == 0, i2c_master.bus),
(lambda a: a[4] == 1, checker_wb)],
register=True)
self.submodules += interconnect
si5324_clock_router = Si5324ClockRouter(platform, sys_clk_freq)
self.submodules += si5324_clock_router
def __init__(self, width):
GrayCounter.__init__(self, width)
###
self.comb += [self.ce.eq(1)]
def __init__(self, width):
GrayCounter.__init__(self, width)
self.input_sig = Signal()
###
self.comb += [self.ce.eq(1)]
def __init__(self, width):
GrayCounter.__init__(self, width)
self.input_sig = Signal()
###
self.comb += [self.ce.eq(1)]
