def __init__(self, platform, eba_reset):
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
###
i_adr_o = Signal(32)
d_adr_o = Signal(32)
self.specials += Instance("lm32_cpu",
p_eba_reset=Instance.PreformattedParam(
"32'h{:08x}".format(eba_reset)),
i_clk_i=ClockSignal(),
i_rst_i=ResetSignal(),
i_interrupt=self.interrupt,
o_I_ADR_O=i_adr_o,
o_I_DAT_O=i.dat_w,
o_I_SEL_O=i.sel,
o_I_CYC_O=i.cyc,
o_I_STB_O=i.stb,
o_I_WE_O=i.we,
o_I_CTI_O=i.cti,
o_I_BTE_O=i.bte,
i_I_DAT_I=i.dat_r,
i_I_ACK_I=i.ack,
i_I_ERR_I=i.err,
i_I_RTY_I=0,
o_D_ADR_O=d_adr_o,
o_D_DAT_O=d.dat_w,
o_D_SEL_O=d.sel,
o_D_CYC_O=d.cyc,
o_D_STB_O=d.stb,
o_D_WE_O=d.we,
o_D_CTI_O=d.cti,
o_D_BTE_O=d.bte,
i_D_DAT_I=d.dat_r,
i_D_ACK_I=d.ack,
i_D_ERR_I=d.err,
i_D_RTY_I=0)
self.comb += [
self.ibus.adr.eq(i_adr_o[2:]),
self.dbus.adr.eq(d_adr_o[2:])
]
# add Verilog sources
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)),
"verilog")
platform.add_sources(
os.path.join(vdir, "submodule",
"rtl"), "lm32_cpu.v", "lm32_instruction_unit.v",
"lm32_decoder.v", "lm32_load_store_unit.v", "lm32_adder.v",
"lm32_addsub.v", "lm32_logic_op.v", "lm32_shifter.v",
"lm32_multiplier.v", "lm32_mc_arithmetic.v", "lm32_interrupt.v",
"lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", "lm32_dcache.v",
"lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
platform.add_verilog_include_path(vdir)
def __init__(self, platform, eba_reset):
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
###
i_adr_o = Signal(32)
d_adr_o = Signal(32)
self.specials += Instance("lm32_cpu",
p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
i_clk_i=ClockSignal(),
i_rst_i=ResetSignal(),
i_interrupt=self.interrupt,
o_I_ADR_O=i_adr_o,
o_I_DAT_O=i.dat_w,
o_I_SEL_O=i.sel,
o_I_CYC_O=i.cyc,
o_I_STB_O=i.stb,
o_I_WE_O=i.we,
o_I_CTI_O=i.cti,
o_I_BTE_O=i.bte,
i_I_DAT_I=i.dat_r,
i_I_ACK_I=i.ack,
i_I_ERR_I=i.err,
i_I_RTY_I=0,
o_D_ADR_O=d_adr_o,
o_D_DAT_O=d.dat_w,
o_D_SEL_O=d.sel,
o_D_CYC_O=d.cyc,
o_D_STB_O=d.stb,
o_D_WE_O=d.we,
o_D_CTI_O=d.cti,
o_D_BTE_O=d.bte,
i_D_DAT_I=d.dat_r,
i_D_ACK_I=d.ack,
i_D_ERR_I=d.err,
i_D_RTY_I=0)
self.comb += [
self.ibus.adr.eq(i_adr_o[2:]),
self.dbus.adr.eq(d_adr_o[2:])
]
# add Verilog sources
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_source_dir(os.path.join(vdir, "submodule", "rtl"))
def __init__(self, size=1, adr_width=30):
self.i1 = wishbone.Interface(data_width=32, adr_width=adr_width)
self.i2 = wishbone.Interface(data_width=32, adr_width=adr_width)
# # #
values = Array([Signal(32) for _ in range(size)])
for i in self.i1, self.i2:
self.sync += [
i.dat_r.eq(values[i.adr[:bits_for(size - 1)]]),
i.ack.eq(0),
If(i.cyc & i.stb & ~i.ack, i.ack.eq(1),
If(i.we, values[i.adr[:bits_for(size - 1)]].eq(i.dat_w)))
]
def __init__(self):
self.i1 = wishbone.Interface()
self.i2 = wishbone.Interface()
# # #
value = Signal(32)
for i in self.i1, self.i2:
self.sync += [
i.dat_r.eq(value),
i.ack.eq(0),
If(i.cyc & i.stb & ~i.ack, i.ack.eq(1),
If(i.we, value.eq(i.dat_w)))
]
def __init__(self, size=1):
self.i1 = wishbone.Interface()
self.i2 = wishbone.Interface()
# # #
values = Array([Signal(32) for _ in range(size)])
for i in self.i1, self.i2:
self.sync += [
i.dat_r.eq(values[i.adr]),
i.ack.eq(0),
If(i.cyc & i.stb & ~i.ack, i.ack.eq(1),
If(i.we, values[i.adr].eq(i.dat_w)))
]
def __init__(self, platform, cpu_reset_address, variant="VexRiscv_IMA"):
cpu_dw = {
"VexRiscv_G" : 64,
"VexRiscv_IMA" : 32,
"VexRiscv_IMA_wide" : 64
}[variant]
adr_width = 32-log2_int(cpu_dw//8)
self.ibus = i = wishbone.Interface(data_width=cpu_dw, adr_width=adr_width)
self.dbus = d = wishbone.Interface(data_width=cpu_dw, adr_width=adr_width)
self.endianness = "little"
self.interrupt = Signal(32)
self.specials += Instance(variant,
i_clk=ClockSignal(),
i_reset=ResetSignal(),
i_externalResetVector=cpu_reset_address,
i_externalInterruptArray=self.interrupt,
i_timerInterrupt=0,
o_iBusWishbone_ADR=i.adr,
o_iBusWishbone_DAT_MOSI=i.dat_w,
o_iBusWishbone_SEL=i.sel,
o_iBusWishbone_CYC=i.cyc,
o_iBusWishbone_STB=i.stb,
o_iBusWishbone_WE=i.we,
o_iBusWishbone_CTI=i.cti,
o_iBusWishbone_BTE=i.bte,
i_iBusWishbone_DAT_MISO=i.dat_r,
i_iBusWishbone_ACK=i.ack,
i_iBusWishbone_ERR=i.err,
o_dBusWishbone_ADR=d.adr,
o_dBusWishbone_DAT_MOSI=d.dat_w,
o_dBusWishbone_SEL=d.sel,
o_dBusWishbone_CYC=d.cyc,
o_dBusWishbone_STB=d.stb,
o_dBusWishbone_WE=d.we,
o_dBusWishbone_CTI=d.cti,
o_dBusWishbone_BTE=d.bte,
i_dBusWishbone_DAT_MISO=d.dat_r,
i_dBusWishbone_ACK=d.ack,
i_dBusWishbone_ERR=d.err)
# add Verilog sources
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_source(os.path.join(vdir, variant+".v"))
def __init__(self):
self.sink = sink = stream.Endpoint(etherbone_mmap_description(32))
self.source = source = stream.Endpoint(etherbone_mmap_description(32))
self.bus = bus = wishbone.Interface()
# # #
data = Signal(32)
data_update = Signal()
self.sync += If(data_update, data.eq(bus.dat_r))
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act(
"IDLE", sink.ack.eq(1),
If(
sink.stb, sink.ack.eq(0),
If(sink.we,
NextState("WRITE_DATA")).Else(NextState("READ_DATA"))))
fsm.act(
"WRITE_DATA", bus.adr.eq(sink.addr), bus.dat_w.eq(sink.data),
bus.sel.eq(sink.be), bus.stb.eq(sink.stb), bus.we.eq(1),
bus.cyc.eq(1),
If(bus.stb & bus.ack, sink.ack.eq(1),
If(sink.eop, NextState("IDLE"))))
fsm.act(
"READ_DATA", bus.adr.eq(sink.addr), bus.sel.eq(sink.be),
bus.stb.eq(sink.stb), bus.cyc.eq(1),
If(bus.stb & bus.ack, data_update.eq(1), NextState("SEND_DATA")))
fsm.act(
"SEND_DATA", source.stb.eq(sink.stb), source.eop.eq(sink.eop),
source.base_addr.eq(sink.base_addr), source.addr.eq(sink.addr),
source.count.eq(sink.count), source.be.eq(sink.be),
source.we.eq(1), source.data.eq(data),
If(source.stb & source.ack, sink.ack.eq(1),
If(source.eop, NextState("IDLE")).Else(NextState("READ_DATA"))))
def __init__(self, dwidth=32, awidth=30):
self.adr = Signal(awidth)
self.dat_w = Signal(dwidth)
self.dat_r = Signal(dwidth)
self.we = Signal(1)
self.sel = Signal(int(dwidth / 8))
self.stb = Signal(1)
self.ack = Signal(1)
self.cyc = Signal(1)
self.cti = Signal(3)
self.bte = Signal(2)
self.err = Signal(1)
from misoc.interconnect import wishbone
self.bus = bus = wishbone.Interface()
self.comb += (
self.bus.adr.eq(self.adr),
self.bus.dat_w.eq(self.dat_w),
self.bus.we.eq(self.we),
self.bus.sel.eq(self.sel),
self.bus.stb.eq(self.stb),
self.bus.cyc.eq(self.cyc),
self.bus.cti.eq(self.cti),
self.bus.bte.eq(self.bte),
self.dat_r.eq(self.bus.dat_r),
self.ack.eq(self.bus.ack),
self.err.eq(self.bus.err),
)
def __init__(self,
platform,
exec_address=0x45000000,
main_mem_origin=0x40000000,
l2_size=8192):
self._reset = CSRStorage(reset=1)
# # #
# CPU core
self.clock_domains.cd_sys_kernel = ClockDomain()
self.comb += [
self.cd_sys_kernel.clk.eq(ClockSignal()),
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
kasli_v1 = isinstance(
platform, kasli.Platform) and platform.hw_rev in ("v1.0", "v1.1")
self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
vexriscv.VexRiscv(
platform,
exec_address,
variant="VexRiscv_IMA" if kasli_v1 else "VexRiscv_G"))
self.cpu_dw = len(self.cpu.dbus.dat_w)
self._wb_slaves = WishboneSlaveManager(0x80000000, dw=self.cpu_dw)
# DRAM access
self.wb_sdram = wishbone.Interface(data_width=self.cpu_dw,
adr_width=32 -
log2_int(self.cpu_dw // 8))
self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram)
def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big"):
self.sink = stream.Endpoint(eth_phy_layout(dw))
self.source = stream.Endpoint(eth_phy_layout(dw))
self.bus = wishbone.Interface(data_width=dw, adr_width=32-log2_int(dw//8))
# # #
# storage in SRAM
sram_depth = eth_mtu//(dw//8)
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness)
self.comb += [
self.sink.connect(self.sram.sink),
self.sram.source.connect(self.source)
]
# Wishbone interface
wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True, data_width=dw)
for n in range(nrxslots)]
# TODO: FullMemoryWE should move to Mibuild
wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False, data_width=dw))
for n in range(ntxslots)]
wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
wb_slaves = []
decoderoffset = log2_int(sram_depth, need_pow2=False)
decoderbits = log2_int(len(wb_sram_ifs))
for n, wb_sram_if in enumerate(wb_sram_ifs):
def slave_filter(a, v=n):
return a[decoderoffset:decoderoffset+decoderbits] == v
wb_slaves.append((slave_filter, wb_sram_if.bus))
self.submodules += wb_sram_if
wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
self.submodules += wb_con
def __init__(self, platform,
exec_address=0x40800000,
main_mem_origin=0x40000000,
l2_size=8192):
self._reset = CSRStorage(reset=1)
# # #
self._wb_slaves = WishboneSlaveManager(0x80000000)
# CPU core
self.clock_domains.cd_sys_kernel = ClockDomain()
self.comb += [
self.cd_sys_kernel.clk.eq(ClockSignal()),
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
mor1kx.MOR1KX(
platform,
OPTION_RESET_PC=exec_address,
FEATURE_PERFCOUNTERS="ENABLED",
OPTION_PERFCOUNTERS_NUM=7))
# DRAM access
self.wb_sdram = wishbone.Interface()
self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram)
def __init__(self, ws):
sequence = [b for write in test_writes for b in encode_record(*write)]
sequence.append(0)
sequence = pack(sequence, ws)
bus = wishbone.Interface(ws * 8)
self.submodules.memory = wishbone.SRAM(1024, init=sequence, bus=bus)
self.submodules.dut = dma.DMA(bus)
def __init__(self, pads, bus=None):
if bus is None:
bus = wishbone.Interface(data_width=32)
self.bus = bus
###
# Wishbone
self.submodules.i2c = i2c = I2CMasterMachine(clock_width=20)
self.sync += [
# read
If(
bus.adr[0],
bus.dat_r.eq(i2c.cg.load),
).Else(bus.dat_r.eq(Cat(i2c.data, i2c.ack, C(0, 4), i2c.idle)), ),
# write
i2c.read.eq(0),
i2c.write.eq(0),
i2c.start.eq(0),
i2c.stop.eq(0),
bus.ack.eq(0),
If(
bus.cyc & bus.stb & ~bus.ack, bus.ack.eq(1),
If(
bus.we,
If(
bus.adr[0],
i2c.cg.load.eq(bus.dat_w),
).Else(
i2c.data.eq(bus.dat_w[0:8]),
i2c.ack.eq(bus.dat_w[8]),
i2c.read.eq(bus.dat_w[9]),
i2c.write.eq(bus.dat_w[10]),
i2c.start.eq(bus.dat_w[11]),
i2c.stop.eq(bus.dat_w[12]),
)))
]
# I/O
self.scl_t = TSTriple()
self.specials += self.scl_t.get_tristate(pads.scl)
self.comb += [
self.scl_t.oe.eq(~i2c.scl_o),
self.scl_t.o.eq(0),
]
self.sda_t = TSTriple()
self.specials += self.sda_t.get_tristate(pads.sda)
self.comb += [
self.sda_t.oe.eq(~i2c.sda_o),
self.sda_t.o.eq(0),
i2c.sda_i.eq(self.sda_t.i),
]
def __init__(self, platform, cpu_reset_address):
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
self.specials += Instance("VexRiscv",
i_clk=ClockSignal(),
i_reset=ResetSignal(),
i_externalResetVector=cpu_reset_address,
i_externalInterruptArray=self.interrupt,
i_timerInterrupt=0,
o_iBusWishbone_ADR=i.adr,
o_iBusWishbone_DAT_MOSI=i.dat_w,
o_iBusWishbone_SEL=i.sel,
o_iBusWishbone_CYC=i.cyc,
o_iBusWishbone_STB=i.stb,
o_iBusWishbone_WE=i.we,
o_iBusWishbone_CTI=i.cti,
o_iBusWishbone_BTE=i.bte,
i_iBusWishbone_DAT_MISO=i.dat_r,
i_iBusWishbone_ACK=i.ack,
i_iBusWishbone_ERR=i.err,
o_dBusWishbone_ADR=d.adr,
o_dBusWishbone_DAT_MOSI=d.dat_w,
o_dBusWishbone_SEL=d.sel,
o_dBusWishbone_CYC=d.cyc,
o_dBusWishbone_STB=d.stb,
o_dBusWishbone_WE=d.we,
o_dBusWishbone_CTI=d.cti,
o_dBusWishbone_BTE=d.bte,
i_dBusWishbone_DAT_MISO=d.dat_r,
i_dBusWishbone_ACK=d.ack,
i_dBusWishbone_ERR=d.err)
# add Verilog sources
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_sources(os.path.join(vdir), "VexRiscv.v")
platform.add_verilog_include_path(vdir)
def register_kernel_cpu_csrdevice(self, name, csrs=None):
if csrs is None:
csrs = getattr(self, name).get_csrs()
csr_bus = wishbone.Interface(data_width=32,
adr_width=32 -
log2_int(self.csr_separation))
bank = wishbone.CSRBank(csrs, bus=csr_bus)
self.submodules += bank
self.kernel_cpu.add_wb_slave(self.mem_map[name],
self.csr_separation * 2**bank.decode_bits,
bank.bus)
self.add_csr_region(name, self.mem_map[name] | 0x80000000, 32, csrs)
def __init__(self, ws):
sequence1 = encode_sequence(test_writes1, ws)
sequence2 = encode_sequence(test_writes2, ws)
offset = 512 // ws
assert len(sequence1) < offset
sequence = (sequence1 + [
prng.randrange(2**(ws * 8)) for _ in range(offset - len(sequence1))
] + sequence2)
bus = wishbone.Interface(ws * 8)
self.submodules.memory = wishbone.SRAM(1024, init=sequence, bus=bus)
self.submodules.dut = dma.DMA(bus)
def __init__(self, link_layer):
self.bus = wishbone.Interface()
self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w))
self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w))
tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False)
rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
wsb = log2_int(len(self.bus.dat_w)//8)
decoder = wishbone.Decoder(self.bus,
[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus),
(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)],
register=True)
self.submodules += tx_sdram_if, rx_sdram_if, decoder
def get_native_sdram_if(self):
"""Creates and registers a native SDRAM interface, tightly coupled to
the controller.
This can only be called after ``register_sdram``.
"""
if isinstance(self.sdram_controller, minicon.Minicon):
bus = wishbone.Interface(len(self.sdram_controller.bus.dat_w))
self._native_sdram_ifs.append(bus)
return bus
elif isinstance(self.sdram_controller, lasmicon.LASMIcon):
return self.lasmi_crossbar.get_master()
else:
raise TypeError
def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
SoCCore.__init__(self,
platform,
clk_freq,
integrated_main_ram_size=0,
**kwargs)
self.csr_devices += ["dfii", "l2_cache"]
if l2_size:
self.config["L2_SIZE"] = l2_size
self.l2_size = l2_size
self._sdram_phy = []
self._cpulevel_sdram_ifs = []
self._cpulevel_sdram_if_arbitrated = wishbone.Interface()
def __init__(self, platform, **kwargs):
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
int_pads, wb_tgt_pads = platform.request("irq"), platform.request(
"wishbone")
self.comb += [int_pads.eq(self.interrupt)]
for (pad_name, width, direction) in wishbone._layout:
if direction == DIR_M_TO_S:
# from init (external) to tgt (us)
self.comb += [
getattr(d, pad_name).eq(getattr(wb_tgt_pads, pad_name))
]
else:
self.comb += [
getattr(wb_tgt_pads, pad_name).eq(getattr(d, pad_name))
]
def __init__(self):
self.wishbone = wb = wishbone.Interface()
self.sys = sys = Record(sys_layout)
###
sys2 = Record(sys_layout)
self.specials += Instance(
"bus_clk_bridge",
i_sys_clk_i=sys.clk,
i_sys_rstn_i=sys.rstn,
i_sys_addr_i=sys.addr,
i_sys_wdata_i=sys.wdata,
i_sys_sel_i=sys.sel,
i_sys_wen_i=sys.wen,
i_sys_ren_i=sys.ren,
o_sys_rdata_o=sys.rdata,
o_sys_err_o=sys.err,
o_sys_ack_o=sys.ack,
i_clk_i=ClockSignal(),
i_rstn_i=~ResetSignal(),
o_addr_o=sys2.addr,
o_wen_o=sys2.wen,
o_ren_o=sys2.ren,
o_wdata_o=sys2.wdata,
i_rdata_i=sys2.rdata,
i_err_i=sys2.err,
i_ack_i=sys2.ack,
)
self.sync += [
If(
sys2.ren | sys2.wen,
wb.cyc.eq(1),
wb.adr.eq(sys2.addr[2:]),
wb.we.eq(sys2.wen),
wb.dat_w.eq(sys2.wdata),
).Elif(wb.ack, wb.cyc.eq(0))
]
self.comb += [
wb.stb.eq(wb.cyc),
sys2.rdata.eq(wb.dat_r),
sys2.ack.eq(wb.ack),
sys2.err.eq(wb.err),
]
def __init__(self, program, bus=None):
if bus is None:
bus = wishbone.Interface()
self.bus = bus
###
assert isinstance(program[-1], InstEnd)
program_e = [encode(inst) for inst in program]
mem = Memory(32, len(program), init=program_e)
self.specials += mem
mem_port = mem.get_port()
self.specials += mem_port
fsm = FSM(reset_state="FETCH")
self.submodules += fsm
i_opcode = mem_port.dat_r[21:23]
i_address = mem_port.dat_r[20:21]
i_data_mask = mem_port.dat_r[0:20]
self.sync += [
self.bus.adr.eq(i_address),
self.bus.sel.eq(1),
self.bus.dat_w.eq(i_data_mask),
]
fsm.act("FETCH", NextState("DECODE"))
fsm.act(
"DECODE",
If(i_opcode == 0b00, NextState("END")).Elif(
i_opcode == 0b01,
NextState("WRITE")).Elif(i_opcode == 0b10, NextState("WAIT")))
fsm.act(
"WRITE", self.bus.cyc.eq(1), self.bus.stb.eq(1), self.bus.we.eq(1),
If(self.bus.ack, NextValue(mem_port.adr, mem_port.adr + 1),
NextState("FETCH")))
fsm.act(
"WAIT", self.bus.cyc.eq(1), self.bus.stb.eq(1),
If(self.bus.ack & ((self.bus.dat_r & i_data_mask) == i_data_mask),
NextValue(mem_port.adr, mem_port.adr + 1), NextState("FETCH")))
fsm.act("END", NextState("END"))
def __init__(self, ws):
self.ttl0 = Signal()
self.ttl1 = Signal()
self.submodules.phy0 = ttl_simple.Output(self.ttl0)
self.submodules.phy1 = ttl_simple.Output(self.ttl1)
rtio_channels = [
rtio.Channel.from_phy(self.phy0),
rtio.Channel.from_phy(self.phy1)
]
sequence = encode_sequence(test_writes_full_stack, ws)
bus = wishbone.Interface(ws * 8)
self.submodules.memory = wishbone.SRAM(256, init=sequence, bus=bus)
self.submodules.dut = dma.DMA(bus)
self.submodules.rtio = rtio.Core(rtio_channels)
self.comb += self.dut.cri.connect(self.rtio.cri)
def __init__(self, bus_wishbone=None, bus_csr=None):
if bus_wishbone is None:
bus_wishbone = wishbone.Interface()
self.wishbone = bus_wishbone
if bus_csr is None:
bus_csr = csr_bus.Interface()
self.csr = bus_csr
###
self.sync += [
self.csr.we.eq(0),
self.csr.dat_w.eq(self.wishbone.dat_w),
self.csr.adr.eq(self.wishbone.adr),
self.wishbone.dat_r.eq(self.csr.dat_r)
]
self.sync += timeline(self.wishbone.cyc & self.wishbone.stb,
[(1, [self.csr.we.eq(self.wishbone.we)]),
(2, [self.wishbone.ack.eq(1)]),
(3, [self.wishbone.ack.eq(0)])])
def __init__(self):
self.bus = bus = wishbone.Interface()
self.ready = Signal(reset=1)
self.sink = sink = stream.Endpoint(etherbone_mmap_description(32))
self.source = source = stream.Endpoint(etherbone_mmap_description(32))
# # #
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act(
"IDLE", sink.ack.eq(1),
If(
bus.stb & bus.cyc,
If(
self.ready,
If(bus.we, NextState("SEND_WRITE")).Else(
NextState("SEND_READ"))).Else(
NextState("SEND_ERROR"))))
fsm.act(
"SEND_WRITE",
If(~self.ready, NextState("SEND_ERROR")).Else(
source.stb.eq(1), source.eop.eq(1),
source.base_addr[2:].eq(bus.adr), source.count.eq(1),
source.be.eq(bus.sel), source.we.eq(1),
source.data.eq(bus.dat_w),
If(source.stb & source.ack, bus.ack.eq(1), NextState("IDLE"))))
fsm.act(
"SEND_READ",
If(~self.ready, NextState("SEND_ERROR")).Else(
source.stb.eq(1), source.eop.eq(1), source.base_addr.eq(0),
source.count.eq(1), source.be.eq(bus.sel), source.we.eq(0),
source.data[2:].eq(bus.adr),
If(source.stb & source.ack, NextState("WAIT_READ"))))
fsm.act(
"WAIT_READ", sink.ack.eq(1),
If(~self.ready,
NextState("SEND_ERROR")).Elif(sink.stb & sink.we, bus.ack.eq(1),
bus.dat_r.eq(sink.data),
NextState("IDLE")))
fsm.act("SEND_ERROR", bus.ack.eq(1), bus.err.eq(1))
def __init__(self,
address_width,
wb=None,
rtio_enable_replace=False,
write_only=False):
if wb is None:
wb = wishbone.Interface()
self.wb = wb
self.rtlink = rtlink.Interface(
rtlink.OInterface(len(wb.dat_w),
address_width +
1 if not write_only else address_width,
enable_replace=rtio_enable_replace),
rtlink.IInterface(len(wb.dat_r), timestamped=False)
if not write_only else None)
# # #
active = Signal()
self.sync.rio += [
If(
self.rtlink.o.stb, active.eq(1),
wb.adr.eq(self.rtlink.o.address[:address_width]),
wb.we.eq(~self.rtlink.o.address[address_width]
if not write_only else 1),
wb.dat_w.eq(self.rtlink.o.data),
wb.sel.eq(2**len(wb.sel) - 1)),
If(wb.ack, active.eq(0))
]
self.comb += [
self.rtlink.o.busy.eq(active),
wb.cyc.eq(active),
wb.stb.eq(active),
]
if not write_only:
self.comb += [
self.rtlink.i.stb.eq(wb.ack & ~wb.we),
self.rtlink.i.data.eq(wb.dat_r)
]
def __init__(self):
self.bus = wishbone.Interface()
self.submodules.jt51 = JT51()
###
bus_cyc = self.bus.stb & self.bus.cyc
# IRQ connection goes to CPU.
self.comb += [
self.jt51.bus.d_in.eq(self.bus.dat_w[0:8]),
# self.bus.dat_r.eq(self.jt51.bus.d_out),
self.bus.dat_r.eq(Replicate(self.jt51.bus.d_out, 4)),
self.jt51.bus.a0.eq(self.bus.adr[0]),
self.jt51.bus.cs_n.eq(~bus_cyc),
self.jt51.bus.wr_n.eq(~self.bus.we)
]
self.sync.ym2151 += [
self.bus.ack.eq(0),
If(bus_cyc & ~self.bus.ack, self.bus.ack.eq(1)),
]
def __init__(self, bus_wishbone=None, bus_csr=None, wb_bus_dw=32):
if bus_wishbone is None:
bus_wishbone = wishbone.Interface(data_width=wb_bus_dw,
adr_width=32 -
log2_int(wb_bus_dw // 8))
self.wishbone = bus_wishbone
if bus_csr is None:
bus_csr = csr_bus.Interface()
self.csr = bus_csr
###
self.sync += [
self.csr.we.eq(0),
self.csr.dat_w.eq(self.wishbone.dat_w),
self.csr.adr.eq(self.wishbone.adr),
self.wishbone.dat_r.eq(self.csr.dat_r)
]
self.sync += timeline(self.wishbone.cyc & self.wishbone.stb,
[(1, [self.csr.we.eq(self.wishbone.we)]),
(2, [self.wishbone.ack.eq(1)]),
(3, [self.wishbone.ack.eq(0)])])
def __init__(self,
platform,
exec_address=0x45000000,
main_mem_origin=0x40000000,
l2_size=8192):
self._reset = CSRStorage(reset=1)
# # #
self._wb_slaves = WishboneSlaveManager(0x80000000)
# CPU core
self.clock_domains.cd_sys_kernel = ClockDomain()
self.comb += [
self.cd_sys_kernel.clk.eq(ClockSignal()),
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
vexriscv.VexRiscv(platform, exec_address))
# DRAM access
self.wb_sdram = wishbone.Interface()
self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram)
def __init__(self,
platform,
exec_address=0x40400000,
main_mem_origin=0x40000000,
l2_size=8192):
self._reset = CSRStorage(reset=1)
# # #
self._wb_slaves = []
# CPU core
self.clock_domains.cd_sys_kernel = ClockDomain()
self.comb += [
self.cd_sys_kernel.clk.eq(ClockSignal()),
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(mor1kx.MOR1KX(
platform, exec_address))
# DRAM access
self.wb_sdram = wishbone.Interface()
self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)
