def parse(self, scf_file):
i = 0
#iterate over the input generating the modules
while i < len(scf_file):
if self.template.modules.get(scf_file[i]):
name = scf_file[i]
lines = []
i += 1
#while does not encounter other module or the end of the file, all the lines belong to this module
while not self.template.modules.get(scf_file[i]) and scf_file[i] != '*END OF' and i < len(scf_file) :
if not is_comment(scf_file[i]) : lines.append(scf_file[i])
i += 1
module = Module(name)
module.parse(self.template, lines)
self.addModule(module)
else:
i += 1
def parse(tkns):
""" Parse a verilog file. Note we currently ignore preprocessor
stuff """
modules = []
while not tkns.at_end():
if tkns.check(Tokens.KW_MODULE):
module = Module.parse(tkns)
modules.append(module)
else:
tkns.next()
return VerilogFile(modules)
