def tb_sumbits():
'''' test-bench for the sumbits() implementation '''
Clk = myhdl.Signal(bool(0))
Reset = myhdl.ResetSignal(0, active=1, async=True)
D = myhdl.Signal(myhdl.intbv(0)[WIDTH_D:])
Q = myhdl.Signal(myhdl.intbv(0)[WIDTH_Q:])
dut = sumbits(Clk, Reset, D, Q)
tCK = 10
ClkCount = myhdl.Signal(myhdl.intbv(0)[8:])
@myhdl.instance
def clkgen():
yield hdlutils.genClk(Clk, tCK, ClkCount)
@myhdl.instance
def resetgen():
yield hdlutils.genReset(Clk, tCK, Reset)
@myhdl.instance
def stimulusin():
yield hdlutils.delayclks(Clk, tCK, 5)
D.next = 0x13
yield hdlutils.delayclks(Clk, tCK, 1)
D.next = 0x01
yield hdlutils.delayclks(Clk, tCK, 1)
D.next = 0x02
yield hdlutils.delayclks(Clk, tCK, 1)
D.next = 0x03
yield hdlutils.delayclks(Clk, tCK, 5)
raise myhdl.StopSimulation
return dut, clkgen, resetgen, stimulusin
def loopback_testbench(fdepth):
assert fdepth >= len(TXRX_DATA), "Error: FIFO depth = {0}. Size of test data: {1}".format(fdepth, len(TXRX_DATA))
clk = createSignal(0, 1)
rst = hdl.ResetSignal(0, active=True, async=False)
rx = createSignal(1, 1)
tx = createSignal(0, 1)
anodos = createSignal(0, 4)
segmentos = createSignal(0, 8)
clk_tout = clk_n_timeout(clk, rst) # noqa
dut = Loopback(clk_i=clk, rst_i=rst, rx_i=rx, tx_o=tx, anodos_o=anodos, segmentos_o=segmentos, # noqa
FIFO_DEPTH=fdepth, CLK_BUS=CLK_XTAL, BAUD_RATE=BAUD)
rx_data = createSignal(0, 8)
rx_buffer = []
def _rx_proc(data):
yield tx.negedge
data.next = 0
yield hdl.delay((CLK_XTAL // (BAUD * 2)) * TICK_PERIOD)
for _ in range(8):
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
data.next = hdl.concat(tx, data[8:1])
yield tx.posedge
def _tx_proc(data, tx):
tx.next = False
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
for i in range(8):
tx.next = (data >> i) & 0x01
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
tx.next = True
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
# --------------------------------------------------------------------------
@hdl.instance
def rx_proc():
for _ in range(len(TXRX_DATA)):
yield _rx_proc(rx_data)
rx_buffer.append(int(rx_data))
print('Received: {}(0x{})'.format(chr(rx_data), rx_data))
yield hdl.delay(5 * (CLK_XTAL // BAUD) * TICK_PERIOD)
print('Buffer: {}'.format(rx_buffer))
assert TXRX_DATA == rx_buffer, "[Loopback Error]: Send: {0}, Received: {1}".format(TXRX_DATA, rx_buffer)
print('[Loopback] Test: OK')
raise hdl.StopSimulation
@hdl.instance
def tx_proc():
yield hdl.delay(2 * (CLK_XTAL // BAUD) * TICK_PERIOD)
for data in TXRX_DATA:
yield _tx_proc(data, rx)
print("Send: {}({})".format(chr(data), hex(data)))
return hdl.instances()
def uart_tx_testbench():
clk = createSignal(0, 1)
rst = hdl.ResetSignal(0, active=True, async=False)
tx_data = createSignal(0, 8)
rx_data = createSignal(0, 8)
tx_start = createSignal(0, 1)
tx_ready = createSignal(0, 1)
rx_ready = createSignal(0, 1)
rx = createSignal(1, 1)
tx = createSignal(0, 1)
rx_check = createSignal(0, 8)
clk_tout = clk_n_timeout(clk, rst) # noqa
dut = UART(
clk,
rst,
tx_data,
tx_start,
tx_ready,
tx, # noqa
rx_data,
rx_ready,
rx,
CLK_BUS=CLK_XTAL,
BAUD_RATE=BAUD)
def _rx_proc(data):
yield tx.negedge
yield hdl.delay((CLK_XTAL // (BAUD * 2)) * TICK_PERIOD)
for _ in range(8):
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
data.next = hdl.concat(tx, data[8:1])
yield tx.posedge
@hdl.instance
def uart_stimulus():
yield tx_ready.posedge
for data in TXRX_DATA:
tx_data.next = data
tx_start.next = True
yield hdl.delay(TICK_PERIOD)
yield _rx_proc(rx_check)
yield tx_ready.posedge
tx_start.next = False
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
assert rx_check == data, "[TX error] Received: {0}. Send: {1}".format(
hex(rx_check), hex(data))
yield hdl.delay((CLK_XTAL // (BAUD * 2)) * TICK_PERIOD)
raise hdl.StopSimulation
return hdl.instances()
def uart_rx_testbench():
clk = createSignal(0, 1)
rst = hdl.ResetSignal(0, active=True, async=False)
tx_data = createSignal(0, 8)
rx_data = createSignal(0, 8)
tx_start = createSignal(0, 1)
tx_ready = createSignal(0, 1)
rx_ready = createSignal(0, 1)
rx = createSignal(1, 1)
tx = createSignal(0, 1)
tx_check = createSignal(0, 8)
clk_tout = clk_n_timeout(clk, rst) # noqa
dut = UART(
clk,
rst,
tx_data,
tx_start,
tx_ready,
tx, # noqa
rx_data,
rx_ready,
rx,
CLK_BUS=CLK_XTAL,
BAUD_RATE=BAUD)
def _tx_proc(data, tx):
tx.next = False
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
for i in range(8):
tx.next = (data >> i) & 0x01
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
tx.next = True
@hdl.instance
def uart_stimulus():
yield hdl.delay(2 * (CLK_XTAL // BAUD) * TICK_PERIOD)
# test RX
for data in TXRX_DATA:
yield _tx_proc(data, rx)
tx_check.next = rx_data
yield hdl.delay(1)
assert tx_check == data, "[RX error] Send: {0}. Received: {1}".format(
hex(data), hex(tx_check))
yield hdl.delay(2 * (CLK_XTAL // BAUD) * TICK_PERIOD)
yield hdl.delay((CLK_XTAL // (BAUD * 2)) * TICK_PERIOD)
raise hdl.StopSimulation
return hdl.instances()
def get_hwgen_args(self):
clock = myhdl.Signal(bool())
reset = myhdl.ResetSignal(bool(True), True, True)
phase_step = myhdl.Signal(myhdl.intbv(0)[self.params.phase_acc_bits:])
BITS = self.params.out_bits
cos_out = myhdl.Signal(myhdl.intbv(0, -2**(BITS - 1), 2**(BITS - 1)))
sin_out = myhdl.Signal(myhdl.intbv(0, -2**(BITS - 1), 2**(BITS - 1)))
# Constants
samples = self.params.fft_samples
args = (clock, reset, phase_step, cos_out, sin_out)
kwargs = {
'PHASE_PRECISION': self.params.phase_bits,
'LUT_DEPTH': self.params.lut_depth,
'DITHER': self.params.phase_dither,
'CORDIC_STAGES': self.params.cordic_stages,
}
return nco.NCOCordic, args, kwargs
def test_rule30():
# We verify that both automata output the same 10 first states
# Note that the bit order is reversed in the two, but that does not really
# matter
INITIAL_STATE = [1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0]
UPDATE_RULE = [0, 1, 1, 1, 1, 0, 0, 0]
reference = rule30_reference.CellularAutomata(UPDATE_RULE,
INITIAL_STATE[::-1])
clock = myhdl.Signal(bool(False))
reset = myhdl.ResetSignal(True, True, True)
state = myhdl.Signal(myhdl.intbv(0)[len(INITIAL_STATE):])
dut = rule30.Rule30(clock, reset, state, INITIAL_STATE, UPDATE_RULE)
@myhdl.always(myhdl.delay(10 / 2))
def advance_clock():
clock.next = not clock
@myhdl.instance
def check_equality():
yield clock.posedge
reset.next = False
yield clock.posedge
# Simply check the initial value and the first couple of transitions
for i in range(10):
ref_state = reference.state[::-1]
for s, ref in zip(state, ref_state):
assert s == ref
yield clock.posedge
reference.update_state()
raise myhdl.StopSimulation()
# Use all instances for simulation
return myhdl.instances()
def uart_loopback_testbench():
clk = createSignal(0, 1)
rst = hdl.ResetSignal(0, active=True, async=False)
tx_data = createSignal(0, 8)
rx_data = createSignal(0, 8)
tx_start = createSignal(0, 1)
tx_ready = createSignal(0, 1)
rx_ready = createSignal(0, 1)
txrx = createSignal(1, 1)
clk_tout = clk_n_timeout(clk, rst) # noqa
dut = UART(
clk,
rst,
tx_data,
tx_start,
tx_ready,
txrx, # noqa
rx_data,
rx_ready,
txrx,
CLK_BUS=CLK_XTAL,
BAUD_RATE=BAUD)
@hdl.instance
def uart_stimulus():
yield hdl.delay(2 * (CLK_XTAL // BAUD) * TICK_PERIOD)
for data in TXRX_DATA:
tx_data.next = data
tx_start.next = True
yield tx_ready.posedge
tx_start.next = False
yield rx_ready.posedge
assert rx_data == data, "[TXRX error] Send: {0}, Received: {1}".format(
hex(data), hex(rx_data))
yield hdl.delay(2 * (CLK_XTAL // BAUD) * TICK_PERIOD)
raise hdl.StopSimulation
return hdl.instances()
def simulation_thread(self):
params = copy.copy(self.params)
clock = myhdl.Signal(bool())
reset = myhdl.ResetSignal(bool(True), True, True)
phase_step = myhdl.Signal(myhdl.intbv(0)[self.params.phase_acc_bits:])
BITS = self.params.out_bits
cos_out = myhdl.Signal(myhdl.intbv(0, -2**(BITS - 1), 2**(BITS - 1)))
sin_out = myhdl.Signal(myhdl.intbv(0, -2**(BITS - 1), 2**(BITS - 1)))
# Constants
samples = self.params.fft_samples
dut = nco.NCOCordic(clock,
reset,
phase_step,
cos_out,
sin_out,
PHASE_PRECISION=self.params.phase_bits,
LUT_DEPTH=self.params.lut_depth,
DITHER=self.params.phase_dither,
CORDIC_STAGES=self.params.cordic_stages)
output = []
@myhdl.always(myhdl.delay(1))
def clockgen():
clock.next = not clock
@myhdl.instance
def simulate():
# A couple of cycles to reset the circuit
reset.next = True
phase_step.next = 0
yield clock.negedge
yield clock.negedge
reset.next = False
phase_step.next = self.params.phase_step
# Flush the pipeline once
for i in range(0, self.params.pipeline_length):
yield clock.negedge
# Now the first correct sample is at the output
for sample in range(0, samples):
time = sample / self.params.frequency
theoretical_phase = (sample / self.params.frequency *
self.params.actual_tone % 1.0) * 2 * np.pi
# Save the result
output.append((time, theoretical_phase, int(cos_out.val),
int(sin_out.val)))
self.emit('simulation_progress', sample / float(samples))
if self._thread_abort:
raise myhdl.StopSimulation("Simulation Aborted")
yield clock.negedge
raise myhdl.StopSimulation
myhdl.Simulation(dut, clockgen, simulate).run(None)
simulation_result = np.array(output, dtype=np.float64)
self.emit('simulation_done', simulation_result, params)
def loopback_testbench(fdepth):
assert fdepth >= len(
TXRX_DATA), "Error: FIFO depth = {0}. Size of test data: {1}".format(
fdepth, len(TXRX_DATA))
clk = createSignal(0, 1)
rst = hdl.ResetSignal(0, active=True, isasync=False)
rx = createSignal(1, 1)
tx = createSignal(0, 1)
anodos = createSignal(0, 4)
segmentos = createSignal(0, 8)
clk_tout = clk_n_timeout(clk, rst) # noqa
dut = Loopback(
clk_i=clk,
rst_i=rst,
rx_i=rx,
tx_o=tx,
anodos_o=anodos,
segmentos_o=segmentos, # noqa
FIFO_DEPTH=fdepth,
CLK_BUS=CLK_XTAL,
BAUD_RATE=BAUD)
rx_data = createSignal(0, 8)
rx_buffer = []
cmd1 = 'iverilog -o build/dut.o build/dut.v build/tb_dut.v'
cmd2 = 'vvp -v -m myhdl build/dut.o'
os.makedirs('./build/', exist_ok=True)
dut.convert(path='./build', name='dut', trace=TRACE, testbench=True)
def compilation():
os.system(cmd1)
return hdl.Cosimulation(cmd2,
clk_i=clk,
rst_i=rst,
rx_i=rx,
tx_o=tx,
anodos_o=anodos,
segmentos_o=segmentos)
def _rx_proc(data):
yield tx.negedge
data.next = 0
yield hdl.delay((CLK_XTAL // (BAUD * 2)) * TICK_PERIOD)
for _ in range(8):
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
data.next = hdl.concat(tx, data[8:1])
yield tx.posedge
def _tx_proc(data, tx):
tx.next = False
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
for i in range(8):
tx.next = (data >> i) & 0x01
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
tx.next = True
yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD)
# --------------------------------------------------------------------------
@hdl.instance
def rx_proc():
for _ in range(len(TXRX_DATA)):
yield _rx_proc(rx_data)
rx_buffer.append(int(rx_data))
print('Received: {}(0x{})'.format(chr(rx_data), rx_data))
yield hdl.delay(5 * (CLK_XTAL // BAUD) * TICK_PERIOD)
print('Buffer: {}'.format(rx_buffer))
assert TXRX_DATA == rx_buffer, "[Loopback Error]: Send: {0}, Received: {1}".format(
TXRX_DATA, rx_buffer)
print('[Loopback-cosimulation] Test: OK')
raise hdl.StopSimulation
@hdl.instance
def tx_proc():
yield hdl.delay(2 * (CLK_XTAL // BAUD) * TICK_PERIOD)
for data in TXRX_DATA:
yield _tx_proc(data, rx)
print("Send: {}({})".format(chr(data), hex(data)))
return hdl.instances(), compilation()
