def simulate():
# A couple of cycles to reset the circuit
reset.next = True
phase_step.next = 0
yield clock.negedge
yield clock.negedge
reset.next = False
phase_step.next = self.params.phase_step
# Flush the pipeline once
for i in range(0, self.params.pipeline_length):
yield clock.negedge
# Now the first correct sample is at the output
for sample in range(0, samples):
time = sample / self.params.frequency
theoretical_phase = (sample / self.params.frequency *
self.params.actual_tone % 1.0) * 2 * np.pi
# Save the result
output.append((time, theoretical_phase, int(cos_out.val),
int(sin_out.val)))
self.emit('simulation_progress', sample / float(samples))
if self._thread_abort:
raise myhdl.StopSimulation("Simulation Aborted")
yield clock.negedge
raise myhdl.StopSimulation
def simulation_time_check():
sim_time_now = myhdl.now()
if sim_time_now > MAX_SIM_TIME:
raise myhdl.StopSimulation(
"Warning! Simulation Exited upon reaching max simulation time of "
+ str(MAX_SIM_TIME) + " clocks")
def receive_data_process():
global recv_data, tap_data_mmult, nbR, acc_out, prediction_res
## Collecting multiplier data
# if (moduleLR0.pipe_multRes.valid == 1):
# if (False == floatDataBus):
# pipe_multRes= moduleLR0.pipe_multRes.data
# else:
# pipe_multRes= (round(float(moduleLR0.pipe_multRes.data),DEF_ROUND))
# tap_mult.extend([pipe_multRes])
displayAccOut(nbR, moduleLR0.pipe_out_acc, 0)
displayAccOut(nbR, moduleLR1.pipe_out_acc, 1)
displayAccOut(nbR, moduleLR2.pipe_out_acc, 2)
displayAccOut(nbR, moduleLR3.pipe_out_acc, 3)
displayAccOut(nbR, moduleLR4.pipe_out_acc, 4)
displayAccOut(nbR, moduleLR5.pipe_out_acc, 5)
displayAccOut(nbR, moduleLR6.pipe_out_acc, 6)
displayAccOut(nbR, moduleLR7.pipe_out_acc, 7)
displayAccOut(nbR, moduleLR8.pipe_out_acc, 8)
displayAccOut(nbR, moduleLR9.pipe_out_acc, 9)
if moduleLR9.pipe_out_acc.valid == 1:
nbR += 1
if nbR == NB_TRAINING_SAMPLES:
prediction_res = (
np.argmax(resY, axis=1) + 1
) # +1 to correct indexing due to speciality of the example. See docs ex3.pdf
for i in range(len(prediction_res)):
prediction_res[i] = (0 if prediction_res[i] == 10 else
prediction_res[i])
print("label: {} prediction: {}".format(label, prediction_res))
raise myhdl.StopSimulation(
"Simulation Finished in %d clks: In total " % myhdl.now() +
str(MAX_NB_TRANSFERS) + " data words transfered")
def putnewdata():
datacount = 0
protocol_ref = tbm_ref.ipcore_ref.get_protocol_ref()
mysrc = tbm_ref.ipcore_ref.router_ref.address
tbm_ref.debug("sourcegen: init dout is %s" % repr(dout.val))
yield myhdl.delay(startdelay)
while True:
if len(data) == datacount:
tbm_ref.debug("sourcegen: end of data. waiting for %d steps" % (period*10))
yield myhdl.delay(period*10)
raise myhdl.StopSimulation("data ended at time %d" % myhdl.now())
dout.next = protocol_ref.newpacket(False, mysrc, mydest, data[datacount])
tbm_ref.debug("sourcegen: data next element %d dout is %s datacount is %d" % (data[datacount], repr(dout.val), datacount))
yield myhdl.delay(period)
datacount += 1
def check_equality():
yield clock.posedge
reset.next = False
yield clock.posedge
# Simply check the initial value and the first couple of transitions
for i in range(10):
ref_state = reference.state[::-1]
for s, ref in zip(state, ref_state):
assert s == ref
yield clock.posedge
reference.update_state()
raise myhdl.StopSimulation()