def _generate_nexys4_board_component():
_set_tovhdl_defaults('nexys4boardcomponent')
toVHDL(nexys4.BoardComponent, spec=_SPEC, clk=_CLK, reset=_RESET,
rx=_UART_RX, tx=_UART_TX, exp_addr=_EXP_ADDR,
exp_data_write=_EXP_DIN, exp_data_read=_EXP_DOUT,
exp_wen=_EXP_WEN, exp_reset=_EXP_RESET, exp_clk=_EXP_CLK,
exp_reset_active=_EXP_RESET_ACTIVE, baudrate=_UART_BAUDRATE)
def _generate_vhdl(output_dir, width_addr, width_data, top_level_file_name, \
exp_reset_active):
toVHDL.std_logic_ports = True
toVHDL.name = os.path.splitext(top_level_file_name)[0]
toVHDL.directory = output_dir
toVHDL.use_clauses = \
'''
Library UNISIM;
use UNISIM.vcomponents.all;
use work.pck_myhdl_090.all;
'''
spec = ControllerSpec(width_addr, width_data)
clk = Signal(False)
reset = ResetSignal(not _RESET_ACTIVE, active=_RESET_ACTIVE, async=False)
rx = Signal(False)
tx = Signal(False)
exp_addr = Signal(intbv(0)[width_addr:0])
exp_din = Signal(intbv(0)[width_data:0])
exp_dout = Signal(intbv(0)[width_data:0])
exp_wen = Signal(False)
exp_reset = Signal(False)
exp_clk = Signal(False)
exp_clk_en = Signal(False)
toVHDL(BoardComponent, spec=spec, clk=clk, reset=reset,
rx=rx, tx=tx, exp_addr=exp_addr, exp_data_write=exp_din,
exp_data_read=exp_dout, exp_wen=exp_wen, exp_reset=exp_reset,
exp_clk=exp_clk, exp_clk_en=exp_clk_en,
exp_reset_active=exp_reset_active, baudrate=_UART_BAUDRATE)
def convert():
q = Signal(intbv(0)[1:0])
d = Signal(intbv(0)[1:0])
wr, rst = [Signal(bool(0)) for i in range(2)]
toVerilog(dff, q, d, wr, rst)
toVHDL(dff, q, d, wr, rst)
def _getCosimulation(self, func, **kwargs):
''' Returns a co-simulation instance of func.
Uses the _simulator specified by self._simulator.
Enables traces if self._trace is True
func - MyHDL function to be simulated
kwargs - dict of func interface assignments: for signals and parameters
'''
vals = {}
vals['topname'] = func.func_name
vals['unitname'] = func.func_name.lower()
hdlsim = self._simulator
if not hdlsim:
raise ValueError("No _simulator specified")
if not self.sim_reg.has_key(hdlsim):
raise ValueError("Simulator {} is not registered".format(hdlsim))
hdl, analyze_cmd, elaborate_cmd, simulate_cmd = self.sim_reg[hdlsim]
# Convert to HDL
if hdl == "verilog":
toVerilog(func, **kwargs)
if self._trace:
self._enableTracesVerilog("./tb_{topname}.v".format(**vals))
elif hdl == "vhdl":
toVHDL(func, **kwargs)
# Analyze HDL
os.system(analyze_cmd.format(**vals))
# Elaborate
if elaborate_cmd:
os.system(elaborate_cmd.format(**vals))
# Simulate
return Cosimulation(simulate_cmd.format(**vals), **kwargs)
def convert():
pins = 10
t = TristateSignal(intbv(1)[pins:])
dir = Signal(bool(0))
wr, rst = [Signal(bool(0)) for i in range(2)]
toVerilog(ReadWriteFlipFlop, t, dir, wr, rst)
toVHDL(ReadWriteFlipFlop, t, dir, wr, rst)
def _generate_controller():
_set_tovhdl_defaults('controller')
toVHDL(Controller, spec=_SPEC, clk=_CLK, reset=_RESET,
rx_fifo_data_read=_RX_FIFO_DOUT, rx_fifo_dequeue=_RX_FIFO_DEQUEUE,
rx_fifo_empty=_RX_FIFO_EMPTY, tx_fifo_data_write=_TX_FIFO_DIN,
tx_fifo_enqueue=_TX_FIFO_ENQUEUE, tx_fifo_full=_TX_FIFO_FULL,
exp_addr=_EXP_ADDR, exp_data_write=_EXP_DIN, exp_data_read=_EXP_DOUT,
exp_wen=_EXP_WEN, exp_reset=_EXP_RESET, exp_clk_en=_EXP_CLK_EN,
exp_reset_active=_EXP_RESET_ACTIVE)
def convert():
Clk = myhdl.Signal(bool(0))
# Reset = myhdl.ResetSignal(0, active=1, async=True)
Reset = None
D = myhdl.Signal(myhdl.intbv(0)[WIDTH_D:])
Q = myhdl.Signal(myhdl.intbv(0)[WIDTH_Q:])
myhdl.toVHDL(sumbits, Clk, Reset, D, Q)
myhdl.toVerilog(sumbits, Clk, Reset, D, Q)
def convert(brd, top=None, name=None, use='verilog', path='.'):
""" Wrapper around the myhdl conversion functions
This function will use the _fpga objects get_portmap function
to map the board definition to the
Arguments
top : top-level myhld module
brd : FPGA board definition (_fpga object)
name : name to use for the generated (converted) file
use : User 'verilog' or 'vhdl' for conversion
path : path of the output files
"""
assert isinstance(brd, _fpga)
name = brd.top_name if name is None else name
pp = brd.get_portmap(top=top)
# convert with the ports and parameters
if use.lower() == 'verilog':
if name is not None:
myhdl.toVerilog.name = name
myhdl.toVerilog(brd.top, **pp)
brd.name = name
brd.vfn = "%s.v"%(name)
elif use.lower() == 'vhdl':
if name is not None:
myhdl.toVHDL.name = name
myhdl.toVHDL(brd.top, **pp)
brd.name = name
brd.vfn = "%s.vhd"%(name)
else:
raise ValueError("Incorrect conversion target %s"%(use))
# make sure the working directory exists
#assert brd.pathexist(brd.path)
time.sleep(2)
# copy files etc to the working directory
tbfn = 'tb_' + brd.vfn
ver = myhdl.__version__
# remove special characters from the version
for sp in ('.', '-', 'dev'):
ver = ver.replace(sp,'')
pckfn = 'pck_myhdl_%s.vhd'%(ver)
for src in (brd.vfn,tbfn,pckfn):
dst = os.path.join(path, src)
print(' checking %s'%(dst))
if os.path.isfile(dst):
print(' removing %s'%(dst))
os.remove(dst)
if os.path.isfile(src):
print(' moving %s --> %s'%(src, path))
try:
shutil.move(src, path)
except Exception,err:
print("skipping %s because %s" % (src, err,))
def convert():
d = Signal(intbv(0)[8:])
q = Signal(intbv(0)[8:])
raddr = Signal(intbv(0)[10:])
waddr = Signal(intbv(0)[10:])
clk = Signal(bool(0))
we = Signal(bool(0))
HeaderRam(d, waddr, raddr, we, clk, q)
myhdl.toVHDL.numeric_ports = False
myhdl.toVHDL(HeaderRam, d, waddr, raddr, we, clk, q)
def tb_convert(toplevel, *ports, **params):
if not os.path.isdir('output/ver/'):
os.makedirs('output/ver/')
myhdl.toVerilog.directory = 'output/ver/'
myhdl.toVerilog(toplevel, *ports, **params)
if not os.path.isdir('output/vhd/'):
os.makedirs('output/vhd/')
myhdl.toVHDL.directory = 'output/vhd/'
myhdl.toVHDL(toplevel, *ports, **params)
def convert(): clk = Signal(bool(False)) reset = ResetSignal(bool(False), bool(True), async=True) en = Signal(bool(True)) F = Signal(intbv(0b0, 0b0, 0b10000)) D = Signal(intbv(0b0, 0b0, 0b10000)) Q = Signal(intbv(0b0, 0b0, 0b10000)) A = Signal(bool(False)) B = Signal(bool(False)) A_latch = Signal(bool(False)) B_latch = Signal(bool(False)) LED = Signal(intbv(0b0, 0b0, 0b10000)) toVerilog.timescale = "100ms/1ms" toVerilog(elevator, clk, reset, en, F, D, Q, A, B, A_latch, B_latch, LED) toVHDL(elevator, clk, reset, en, F, D, Q, A, B, A_latch, B_latch, LED)
def testBench():
i_in, pc_in, i_out, pc_out = [Signal(intbv(0)[32:]) for i in range(4)]
clk, rst, stall = [Signal(intbv(0)[1:]) for i in range(3)]
latch_inst = toVHDL(latch_if_id, clk, rst, i_in, pc_in, i_out, pc_out, stall)
@instance
def stimulus():
for i in range(10):
i_in.next, pc_in.next = [Signal(intbv(random.randint(0, 255))[32:]) for i in range(2)]
if random.random() > 0.10:
clk.next = 1
if random.random() > 0.75:
rst.next = 1
if random.random() > 0.5:
stall.next = 1
yield delay(1)
print "Inputs: %i %i | clk: %i rst: %i stall:%i | Output: %i %i" % (i_in, pc_in, clk, rst, stall, i_out, pc_out)
clk.next = 0
rst.next = 0
stall.next = 0
yield delay(1)
return instances()
def testBench():
branch_adder_in, alu_result_in, data2_in, wr_reg_in = [Signal(intbv(random.randint(-255, 255), min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(4)]
branch_adder_out, alu_result_out, data2_out, wr_reg_out = [Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(4)]
zero_in, zero_out = [Signal(intbv(0)[1:]) for i in range(2)]
Branch_in, MemRead_in, MemWrite_in = [Signal(intbv(0)[1:]) for i in range(3)]
RegWrite_in, MemtoReg_in = [Signal(intbv(0)[1:]) for i in range(2)]
Branch_out, MemRead_out, MemWrite_out = [Signal(intbv(0)[1:]) for i in range(3)]
RegWrite_out, MemtoReg_out = [Signal(intbv(0)[1:]) for i in range(2)]
clk = Signal(intbv(0)[1:])
rst = Signal(intbv(0)[1:])
latch_inst = toVHDL(latch_ex_mem, clk, rst,
branch_adder_in,
alu_result_in, zero_in,
data2_in, wr_reg_in,
Branch_in, MemRead_in, MemWrite_in, # signals to MEM pipeline stage
RegWrite_in, MemtoReg_in, # signals to WB pipeline stage
branch_adder_out,
alu_result_out, zero_out,
data2_out, wr_reg_out,
Branch_out, MemRead_out, MemWrite_out,
RegWrite_out, MemtoReg_out,
)
@instance
def stimulus():
for i in range(5):
if random.random() > 0.25:
clk.next = 1
if random.random() > 0.75:
rst.next = 1
branch_adder_in.next, alu_result_in.next, data2_in.next, wr_reg_in.next = [intbv(random.randint(-255, 255)) for i in range(4)]
Branch_in.next, MemRead_in.next, MemWrite_in.next, zero_in.next = [random.randint(0, 1) for i in range(4)]
RegWrite_in.next, MemtoReg_in.next = [random.randint(0, 1) for i in range(2)]
yield delay(1)
print "-" * 79
print "%i %i %i %i | %i | %i %i %i %i %i " % (branch_adder_in, alu_result_in, data2_in, wr_reg_in, zero_in,
Branch_in, MemRead_in, MemWrite_in,
RegWrite_in, MemtoReg_in)
print "clk: %i rst: %i " % (clk, rst)
print "%i %i %i %i | %i | %i %i %i %i %i " % (branch_adder_out, alu_result_out, data2_out, wr_reg_out, zero_out,
Branch_out, MemRead_out, MemWrite_out,
RegWrite_out, MemtoReg_out)
clk.next = 0
rst.next = 0
yield delay(1)
return instances()
def testBench():
if not DEBUG:
datapath_i = toVHDL(datapath)
else:
datapath_i = datapath()
return instances()
def Convert(self, W=None):
"""Convert the HDL description to Verilog and VHDL.
"""
clk = Signal(False)
ts = Signal(False)
x = Signal(intbv(0,min=-2**(self.W[0]-1), max=2**(self.W[0]-1)))
y = Signal(intbv(0,min=-2**(self.W[0]-1), max=2**(self.W[0]-1)))
if self.isSos:
print("Convert IIR SOS to Verilog and VHDL")
toVerilog(siir_sos_hdl, clk, x, y, ts, A=self.fxa, B=self.fxb, W=self.W)
toVHDL(siir_sos_hdl, clk, x, y, ts, A=self.fxa, B=self.fxb, W=self.W)
else:
# Convert to Verilog and VHDL
print("Convert IIR to Verilog and VHDL")
toVerilog(siir_hdl, clk, x, y, ts, A=self.fxa, B=self.fxb, W=self.W)
toVHDL(siir_hdl, clk, x, y, ts, A=self.fxa, B=self.fxb, W=self.W)
def setUp(self):
self.Rt_ex, self.Rs_id, self.Rt_id = [Signal(intbv(0)[5:]) for i in range(3)]
self.MemRead_ex, self.Stall = [Signal(intbv(0)[1:]) for i in range(2)]
self.detector_ = toVHDL(hazard_detector, self.MemRead_ex, self.Rt_ex,
self.Rs_id, self.Rt_id,
self.Stall
)
def setUp(self):
self.Rd_mem, self.Rs_ex, self.Rt_ex, self.Rd_wb = [ Signal(intbv(0)[5:]) for i in range(4) ]
self.RegWrite_mem, self.RegWrite_wb = [ Signal(intbv(0)[1:]) for i in range(2) ]
self.ForwardA, self.ForwardB = [ Signal(intbv(0)[2:]) for i in range(2) ]
self.forwarding_ = toVHDL(forwarding, self.RegWrite_mem, self.Rd_mem, self.Rs_ex, self.Rt_ex, #inputs of EX hazards
self.RegWrite_wb, self.Rd_wb, #left inputs of MEM hazards
self.ForwardA, self.ForwardB
)
def testBench(args):
global DEBUG
DEBUG = args.debug
data_mem = load_data_memory(args.data) if args.data else None
program = args.program
Clk = Signal(intbv(0)[1:]) # internal clock
clk_driver = clock_driver(Clk, 1)
if args.vcd:
datapath_i = traceSignals(dlx, Clk, program=program, data_mem=data_mem) # () #toVHDL(datapath)
elif args.debug:
datapath_i = dlx(Clk, program=program, data_mem=data_mem)
elif args.to_vhdl:
toVHDL(dlx, Clk, program=program, data_mem=data_mem)
elif args.to_verilog:
toVerilog(dlx, Clk, program=program, data_mem=data_mem)
return instances()
def convert():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
lcd_on = Signal(bool(0))
lcd_resetn = Signal(bool(0))
lcd_csn = Signal(bool(0))
lcd_rs = Signal(bool(0))
lcd_wrn = Signal(bool(0))
lcd_rdn = Signal(bool(0))
lcd_data = Signal(intbv(0)[16:])
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(mm_lt24lcdsys, clock, reset,
lcd_on, lcd_resetn, lcd_csn, lcd_rs,
lcd_wrn, lcd_rdn, lcd_data)
myhdl.toVHDL.directory = 'output'
myhdl.toVHDL(mm_lt24lcdsys, clock, reset,
lcd_on, lcd_resetn, lcd_csn, lcd_rs,
lcd_wrn, lcd_rdn, lcd_data)
tb_move_generated_files()
def TestBench(CounterTester):
count = Signal(intbv(0, min = -2**3, max = 2**3))
clk = Signal(LOW)
inc_or_dec = Signal(HIGH)
wrap_around = Signal(LOW)
rst_n = Signal(HIGH)
# instanciate modules
Counter_inst = toVHDL(Counter, count, clk, inc_or_dec, wrap_around, rst_n)
CounterTester_inst = CounterTester(count, clk, inc_or_dec, wrap_around, rst_n)
ClkGen_inst = ClkGen(clk)
return Counter_inst, CounterTester_inst, ClkGen_inst
def TestBench(ControlSystemManagerTester):
# create fake consign filter
consign_filter_input = Signal(intbv(0, min = -2**30, max = 2**30)) # 31-bit
consign_filter_output = Signal(intbv(0, min = -2**30, max = 2**30)) # 31-bit
@always_comb
def fake_consign_filter():
consign_filter_output.next = consign_filter_input
# create fake correct filter
correct_filter_input = Signal(intbv(0, min = -2**31, max = 2**31)) # 32-bit
correct_filter_output = Signal(intbv(0, min = -2**31, max = 2**31)) # 32-bit
@always_comb
def fake_correct_filter():
correct_filter_output.next = correct_filter_input
# create fake feedback filter
feedback_filter_input = Signal(intbv(0, min = -2**30, max = 2**30)) # 31-bit
feedback_filter_output = Signal(intbv(0, min = -2**30, max = 2**30)) # 31-bit
@always_comb
def fake_feedback_filter():
feedback_filter_output.next = feedback_filter_input
# create fake process
process_input = Signal(intbv(0, min = -2**31, max = 2**31)) # 32-bit
process_output = Signal(intbv(0, min = -2**30, max = 2**30)) # 31-bit
@always_comb
def fake_process():
process_output.next = process_input
# control system inputs
consign = Signal(intbv(0, min = -2**30, max = 2**30)) # 31-bit
# instanciate modules
ControlSystemManager_inst = toVHDL(
ControlSystemManager,
consign_filter_input, consign_filter_output,
correct_filter_input, correct_filter_output,
feedback_filter_input, feedback_filter_output,
process_input, process_output, consign)
ControlSystemManagerTester_inst = ControlSystemManagerTester(
consign_filter_input, consign_filter_output,
correct_filter_input, correct_filter_output,
feedback_filter_input, feedback_filter_output,
process_input, process_output, consign)
return (fake_consign_filter,
fake_correct_filter,
fake_feedback_filter,
fake_process,
ControlSystemManager_inst,
ControlSystemManagerTester_inst)
def TestBench(AngleDistanceToLeftRightTester):
# create 31-bit signed (angle, distance) input signals
angle_val = Signal(intbv(0, min = -2**30, max = 2**30))
distance_val = Signal(intbv(0, min = -2**30, max = 2**30))
# create 32-bit signed (left, right) output signals
left_val = Signal(intbv(0, min = -2**31, max = 2**31))
right_val = Signal(intbv(0, min = -2**31, max = 2**31))
# instanciate modules
AngleDistanceToLeftRight_inst = toVHDL(AngleDistanceToLeftRight, angle_val, distance_val, left_val, right_val)
AngleDistanceToLeftRightTester_inst = AngleDistanceToLeftRightTester(angle_val, distance_val, left_val, right_val)
return AngleDistanceToLeftRight_inst, AngleDistanceToLeftRightTester_inst
def TestBench(RampTester):
# create input and output 32-bit signals with default values
input = Signal(intbv(0, min = -2**31, max = 2**31))
output = Signal(intbv(0, min = -2**31, max = 2**31))
# create max acceleration and deceleration signals with custom values
var_1st_ord_pos = Signal(intbv(13)[32:])
var_1st_ord_neg = Signal(intbv(42)[32:])
# instanciate modules
RampFilter_inst = toVHDL(RampFilter, input, output, var_1st_ord_pos, var_1st_ord_neg)
RampTester_inst = RampTester(input, output, var_1st_ord_pos, var_1st_ord_neg)
return RampFilter_inst, RampTester_inst
def TestBench(LeftRightToAngleDistanceTester):
# create 32-bit signed (left, right) input signals
left_val = Signal(intbv(0, min = -2**31, max = 2**31))
right_val = Signal(intbv(0, min = -2**31, max = 2**31))
# create 32-bit signed (angle, distance) output signals
angle_val = Signal(intbv(0, min = -2**31, max = 2**31))
distance_val = Signal(intbv(0, min = -2**31, max = 2**31))
# instanciate modules
LeftRightToAngleDistance_inst = toVHDL(LeftRightToAngleDistance, left_val, right_val, angle_val, distance_val)
LeftRightToAngleDistanceTester_inst = LeftRightToAngleDistanceTester(left_val, right_val, angle_val, distance_val)
return LeftRightToAngleDistance_inst, LeftRightToAngleDistanceTester_inst
def testBench():
ram_in, alu_result_in, wr_reg_in = [Signal(intbv(random.randint(-255, 255), min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(3)]
ram_out, alu_result_out, wr_reg_out = [Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(3)]
RegWrite_in, MemtoReg_in = [Signal(intbv(0)[1:]) for i in range(2)]
RegWrite_out, MemtoReg_out = [Signal(intbv(0)[1:]) for i in range(2)]
clk = Signal(intbv(0)[1:])
rst = Signal(intbv(0)[1:])
latch_inst = toVHDL(latch_mem_wb, clk, rst,
ram_in,
alu_result_in,
wr_reg_in,
RegWrite_in, MemtoReg_in, # signals to WB pipeline stage
ram_out,
alu_result_out,
wr_reg_out,
RegWrite_out, MemtoReg_out, # signals to WB pipeline stage
)
@instance
def stimulus():
for i in range(5):
if random.random() > 0.25:
clk.next = 1
if random.random() > 0.75:
rst.next = 1
ram_in.next, alu_result_in.next, wr_reg_in.next = [intbv(random.randint(-255, 255)) for i in range(3)]
RegWrite_in.next, MemtoReg_in.next = [random.randint(0, 1) for i in range(2)]
yield delay(1)
print "-" * 79
print "%i %i %i | %i %i " % (ram_in, alu_result_in, wr_reg_in,
RegWrite_in, MemtoReg_in)
print "clk: %i rst: %i " % (clk, rst)
print "%i %i %i | %i %i " % (ram_out, alu_result_out, wr_reg_out,
RegWrite_out, MemtoReg_out)
clk.next = 0
rst.next = 0
yield delay(1)
return instances()
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog.no_testbench = True
myhdl.toVHDL.directory = 'output'
# convert the generator
myhdl.toVerilog(prbs_generate, glbl, prbs, order=23)
myhdl.toVHDL(prbs_generate, glbl, prbs, order=23)
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
myhdl.toVerilog(prbs_check, glbl, prbs, locked,
word_count, error_count, order=23)
myhdl.toVHDL(prbs_check, glbl, prbs, locked,
word_count, error_count, order=23)
def TestBench(PolarMotorsTester):
# create 31-bit signed (angle, distance) input signals
angle_speed = Signal(intbv(0, min = -2**30, max = 2**30))
distance_speed = Signal(intbv(0, min = -2**30, max = 2**30))
# create 32-bit signed (left, right) output signals
left_speed = Signal(intbv(0, min = -2**31, max = 2**31))
right_speed = Signal(intbv(0, min = -2**31, max = 2**31))
# instanciate modules
PolarMotors_inst = toVHDL(PolarMotors, angle_speed, distance_speed,
left_speed, right_speed)
PolarMotorsTester_inst = PolarMotorsTester(angle_speed, distance_speed,
left_speed, right_speed)
return PolarMotors_inst, PolarMotorsTester_inst
def testBench():
I = Signal(intbv(0, min=0, max=16))
O = Signal(intbv(0)[32:])
#pd_instance = prime_detector(E, S)
im_instance = toVHDL(instruction_memory, I, O)
@instance
def stimulus():
for i in range(8):
I.next = intbv(i)
yield delay(10)
print "address: " + bin(I, 4) + " (" + str(I) + ") | instruction: " + bin(O, 32)
return instances()
def TestBench(OdometerTester):
""" Instanciate modules and wire things up.
OdometerTester -- test module to instanciate with OdometerReader and ClkGen
"""
count = Signal(intbv(0, min = -2**10, max=2**10))
a = Signal(LOW)
b = Signal(LOW)
clk = Signal(LOW)
rst_n = Signal(HIGH)
# instanciate modules
OdometerReader_inst = toVHDL(OdometerReader, count, a, b, clk, rst_n)
OdometerTester_inst = OdometerTester(count, a, b, clk, rst_n)
ClkGen_inst = ClkGen(clk)
return OdometerReader_inst, OdometerTester_inst, ClkGen_inst
def testBench():
data_in = Signal(intbv(0, min=-(2 ** 15), max=2 ** 15 - 1))
data_out = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
sign_extend_i = toVHDL(sign_extend, data_in, data_out)
@instance
def stimulus():
for i in range(8):
value = random.randint(-(2 ** 15), 2 ** 15 - 1)
data_in.next = intbv(value, min=-(2 ** 15), max=2 ** 15 - 1)
print "In: %s (%i) | Out: %s (%i)" % (bin(data_in, 16), data_in, bin(data_out, 32), data_out)
yield delay(5)
return instances()
def testBench():
ram_in, alu_result_in, wr_reg_in = [
Signal(intbv(random.randint(-255, 255), min=-(2**31), max=2**31 - 1))
for i in range(3)
]
ram_out, alu_result_out, wr_reg_out = [
Signal(intbv(0, min=-(2**31), max=2**31 - 1)) for i in range(3)
]
RegWrite_in, MemtoReg_in = [Signal(intbv(0)[1:]) for i in range(2)]
RegWrite_out, MemtoReg_out = [Signal(intbv(0)[1:]) for i in range(2)]
clk = Signal(intbv(0)[1:])
rst = Signal(intbv(0)[1:])
latch_inst = toVHDL(
latch_mem_wb,
clk,
rst,
ram_in,
alu_result_in,
wr_reg_in,
RegWrite_in,
MemtoReg_in, #signals to WB pipeline stage
ram_out,
alu_result_out,
wr_reg_out,
RegWrite_out,
MemtoReg_out, #signals to WB pipeline stage
)
@instance
def stimulus():
for i in range(5):
if random.random() > 0.25:
clk.next = 1
if random.random() > 0.75:
rst.next = 1
ram_in.next, alu_result_in.next, wr_reg_in.next = [
intbv(random.randint(-255, 255)) for i in range(3)
]
RegWrite_in.next, MemtoReg_in.next = [
random.randint(0, 1) for i in range(2)
]
yield delay(1)
print("-" * 79)
print("%i %i %i | %i %i " %
(ram_in, alu_result_in, wr_reg_in, RegWrite_in, MemtoReg_in))
print("clk: %i rst: %i " % (clk, rst))
print("%i %i %i | %i %i " % (ram_out, alu_result_out, wr_reg_out,
RegWrite_out, MemtoReg_out))
clk.next = 0
rst.next = 0
yield delay(1)
return instances()
