def setUp(self): self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA) # input signals self.opcode_cmd = Signal(intbv(0)[self.spec.width_opcode:0]) self.rx_ready = Signal(False) self.tx_ready = Signal(False) self.cycle_autonomous = Signal(False) self.reset = ResetSignal(True, active=False, async=False) # output signals self.rx_next = Signal(False) self.opcode_res = Signal(intbv(0)[self.spec.width_message:0]) self.nop = Signal(False) self.exp_wen = Signal(False) self.exp_reset = ResetSignal(True, active=self.EXP_RESET_ACTIVE, async=False) self.cycle_start = Signal(False) self.cycle_pause = Signal(False) self.cycle_step = Signal(False) self.control = ControllerControl(spec=self.spec, reset=self.reset, opcode_cmd=self.opcode_cmd, opcode_res=self.opcode_res, rx_ready=self.rx_ready, rx_next=self.rx_next, tx_ready=self.tx_ready, nop=self.nop, exp_wen=self.exp_wen, exp_reset=self.exp_reset, cycle_autonomous=self.cycle_autonomous, cycle_start=self.cycle_start, cycle_pause=self.cycle_pause, cycle_step=self.cycle_step, exp_reset_active=self.EXP_RESET_ACTIVE)
def __init__(self, rst, wr_clk, rd_clk, factory, depth): # Depth must be a power of two assert depth == depth & ~(depth - 1) self.depth = depth self.factory = factory self.RST = rst # These signals are in the WR_CLK domain self.WR_CLK = wr_clk if self.RST is None: self.WR_RST = None else: self.WR_RST = ResetSignal(True, True, False) self.WR = Signal(False) self.WR_DATA = Signal(factory) self.WR_FULL = Signal(False) # These signals are in the RD_CLK domain self.RD_CLK = rd_clk if self.RST is None: self.RD_RST = None else: self.RD_RST = ResetSignal(True, True, False) self.RD = Signal(False) self.RD_DATA = Signal(factory) self.RD_EMPTY = Signal(False)
def ConvertTransferControlUnit(hdl, path): clk = Signal(bool(0)) rst = ResetSignal(bool(0), bool(1), False) clkEnable = Signal(bool(0)) commStart = Signal(bool(0)) commPause = Signal(bool(0)) commType = Signal(commOpEnum.intbv(commOpEnum.RX)) rxPort = Signal(portTypeEnum.intbv()) txPort = Signal(portTypeEnum.intbv()) dataIn = Signal(intbv(0, -999, 1000)) dataOut = Signal(intbv(0, -999, 1000)) rxLeft = CommInterface(-999, 1000) rxRight = CommInterface(-999, 1000) rxUp = CommInterface(-999, 1000) rxDown = CommInterface(-999, 1000) txLeft = CommInterface(-999, 1000) txRight = CommInterface(-999, 1000) txUp = CommInterface(-999, 1000) txDown = CommInterface(-999, 1000) inst = TransferControlUnit(clk, rst, clkEnable, commStart, commPause, commType, rxPort, txPort, dataIn, dataOut, rxLeft, rxRight, rxUp, rxDown, txLeft, txRight, txUp, txDown) inst.convert(hdl, path=path)
def fifo_async(clock_write, clock_read, fifobus, reset, size=128): """ The following is a general purpose, platform independent asynchronous FIFO (dual clock domains). Cross-clock boundary FIFO, based on: "Simulation and Synthesis Techniques for Asynchronous FIFO Design" Typically in the "rhea" package the FIFOBus interface is used to interface with the FIFOs """ # @todo: use the clock_write and clock_read from the FIFOBus # @todo: interface, make this interface compliant with the # @todo: fifos: fifo_async(reset, clock, fifobus) # for simplification the memory size is forced to a power of # two - full address range, ptr (mem indexes) will wrap asz = int(ceil(log(size, 2))) fbus = fifobus # alias # an extra bit is used to determine full vs. empty (see paper) waddr = Signal(modbv(0)[asz:]) raddr = Signal(modbv(0)[asz:]) wptr = Signal(modbv(0)[asz + 1:]) rptr = Signal(modbv(0)[asz + 1:]) wq2_rptr = Signal(intbv(0)[asz + 1:]) rq2_wptr = Signal(intbv(0)[asz + 1:]) wfull = Signal(bool(0)) rempty = Signal(bool(1)) # sync'd resets, the input reset is more than likely sync'd to one # of the clock domains, sync both regardless ... wrst = ResetSignal(reset.active, active=reset.active, async=reset. async)
def signalSyncBench(DATA=DATA, indata=tuple([i for i in range(2**DATA)])): #n = 2**DATA dIn, dOut = [Signal(intbv(0)[DATA:]) for i in range(2)] clkIn, clkOut = [Signal(bool(0)) for i in range(2)] rst = ResetSignal(0, active=1, isasync=False) clockDriver0_inst = clockDriver(clkIn, DELAY=5) clockDriver1_inst = clockDriver(clkOut, DELAY=7) signalSync_inst = signalSync(clkOut, rst, dIn, dOut, DATA=DATA) @instance def ResetStimulus(): yield delay(15) rst.next = rst.active yield delay(10) rst.next = not rst.active for i in indata: dIn.next = i yield clkIn.posedge print("%d" % dIn, "%d" % dOut) #assert B == B2, "Error occured !!" #assert False, "Error occured !!" raise StopSimulation() return instances()
def setUp(self): self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA) # Input signals self.clk = Signal(False) self.reset = ResetSignal(True, active=False, async=False) self.rx_fifo_data_read = Signal(intbv(0)[8:0]) self.rx_fifo_empty = Signal(False) self.receive_next = Signal(False) # Output signals self.message = Signal(intbv(0)[self.spec.width_message:0]) self.rx_fifo_dequeue = Signal(False) self.message_ready = Signal(False) self.clockgen = ClockGen(self.clk, self.HALF_PERIOD) self.receiver = MessageReceiver( spec=self.spec, clk=self.clk, reset=self.reset, rx_fifo_data_read=self.rx_fifo_data_read, rx_fifo_empty=self.rx_fifo_empty, rx_fifo_dequeue=self.rx_fifo_dequeue, message=self.message, message_ready=self.message_ready, receive_next=self.receive_next)
def c_testbench_two(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=True) ia, ib = MyIntf(), MyIntf() tb_dut = two_level(clock, reset, ia, ib) @instance def tb_clk(): clock.next = False yield delay(10) while True: clock.next = not clock yield delay(10) @instance def tb_stim(): reset.next = False yield delay(17) reset.next = True yield delay(17) for ii in range(7): yield clock.posedge assert ia.x == 5 assert ia.y == 7 print("%d %d %d %d" % (ia.x, ia.y, ib.x, ib.y)) raise StopSimulation return tb_dut, tb_clk, tb_stim
def testbench(): # Input pins din = Signal(bool(1)) reset = ResetSignal(0, active=1, async=True) # Output pins CS = Signal(bool(0)) SYNC = Signal(bool(0)) dout = Signal(bool(1)) SClk1 = Signal(bool(0)) SClk2 = Signal(bool(0)) # FPGA clock pin clock = Signal(bool(0)) # Modules motorgen = motor(clock, CS, SYNC, din, dout, SClk1, SClk2, reset) # CLOCK HALF_PERIOD = delay(round(1/(2*xula_freq)*1e9)) @always(HALF_PERIOD) def clkgen(): clock.next = not clock @instance def stimulus(): for i in range(1000): yield clock.negedge raise StopSimulation return instances()
def test_one_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=False) sdi = Signal(bool(0)) sdo = Signal(bool(0)) nested = Signal(bool(0)) assert analyze(interfaces_top(clock, reset, sdi, sdo, nested)) == 0
def testbench(): sof = Signal(bool(0)) sync_flag = Signal(bool(0)) clk = Signal(bool(0)) reset_n = ResetSignal(1, active=ACTIVE_LOW, async=True) state = Signal(t_state.SEARCH) framer_ctrl_0 = framer_ctrl(sof, state, sync_flag, clk, reset_n) @always(delay(10)) def clkgen(): clk.next = not clk @instance def stimulus(): for i in range(3): yield clk.negedge for n in (12, 8, 8, 4): sync_flag.next = 1 yield clk.negedge sync_flag._next = 0 for i in range(n - 1): yield clk.negedge raise StopSimulation return framer_ctrl_0, clkgen, stimulus
def tb(uart_tx): tx_bit = Signal(bool(1)) tx_valid = Signal(bool(0)) tx_byte = Signal(intbv(0)[8:]) tx_clk = Signal(bool(0)) # tx_rst = Signal(bool(1)) tx_rst = ResetSignal(1, active=0, isasync=True) uart_tx_inst = uart_tx(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst) # toVerilog(uart_tx, tx_bit, tx_valid, tx_byte, tx_clk, tx_rst) @always(delay(10)) def clk_gen(): tx_clk.next = not tx_clk @instance def stimulus(): tx_rst.next = 1 yield delay(100) tx_rst.next = 0 yield delay(100) tx_rst.next = 1 yield delay(100) for v in (0x00, 0xff, 0x55, 0xaa): yield tx_clk.negedge tx_byte.next = v tx_valid.next = 1 yield tx_clk.negedge tx_valid.next = 0 yield delay(16 * 20) raise StopSimulation return clk_gen, stimulus, uart_tx_inst
def c_testbench_three(): """ this will test the use of constants in an inteface as well as top-level interface conversion. """ clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) x = Signal(intbv(3, min=-5000, max=5000)) y = Signal(intbv(4, min=-200, max=200)) intf = IntfWithConstant2() tbdut = top_const(clock, reset, x, y, intf) @instance def tbclk(): clock.next = False while True: yield delay(3) clock.next = not clock @instance def tbstim(): reset.next = reset.active yield delay(33) reset.next = not reset.active yield clock.posedge yield clock.posedge print("x: %d" % (x, )) print("y: %d" % (y, )) assert x == 0 assert y == 0 raise StopSimulation return tbdut, tbclk, tbstim
def TestKB(): dat = Signal(bool(0)) clk = Signal(bool(0)) rst = ResetSignal(bool(0), active=1, isasync=True) code = Signal(intbv(0)[9:]) finish = Signal(bool(0)) inst = PS2Keyboard(code, finish, dat, clk, rst) the_data = [ [0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1], [0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 1]] @instance def stimulus(): print('dat\tcode\t\tfinish') clk.next = 1 yield delay(10) for k in range(2*11): bit = the_data[k//11][k%11] dat.next = bit yield delay(10) clk.next = 0 yield delay(10) clk.next = 1 print(bit, f'{int(code):09b}', int(finish), sep='\t') return instances()
def setUp(self): self.clock = Signal(bool(1)) self.reset = ResetSignal(bool(0), active=1, async=False) self.test_in = Signal(intbv(0)[10:]) self.test_out = Signal(intbv(0)[16:]) self.reset_cycles = 3 # Includes the initial value self.default_args = { 'test_input': self.test_in, 'output': self.test_out, 'reset': self.reset, 'clock': self.clock } self.default_arg_types = { 'test_input': 'random', 'output': 'output', 'reset': 'init_reset', 'clock': 'clock' } self.sim_checker = mock.Mock() def identity_factory(test_input, output, reset, clock): @always_seq(clock.posedge, reset=reset) def identity(): if __debug__: self.sim_checker(copy.copy(test_input.val)) output.next = test_input return identity self.identity_factory = identity_factory
def c_testbench(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=False) a, b, c = Intf(), Intf(), Intf() tb_dut = use_interfaces(clock, reset, a, b, c) @instance def tb_clk(): clock.next = False yield delay(10) while True: clock.next = not clock yield delay(10) @instance def tb_stim(): reset.next = False yield delay(23) reset.next = True yield delay(33) for ii in range(17): print("a: x=%d y=%d z=%d" % (a.x, a.y, a.z,)) print("b: x=%d y=%d z=%d" % (b.x, b.y, b.z,)) print("c: x=%d y=%d z=%d" % (c.x, c.y, c.z,)) yield clock.posedge raise StopSimulation return tb_dut, tb_clk, tb_stim
def convert(args=None): wclk = Signal(bool(0)) datain = Signal(intbv(0)[36:]) src_rdy_i = Signal(bool(0)) dst_rdy_o = Signal(bool(0)) space = Signal(intbv(0)[16:]) rclk = Signal(bool(0)) dataout = Signal(intbv(0)[36:]) src_rdy_o = Signal(bool(0)) dst_rdy_i = Signal(bool(0)) occupied = Signal(intbv(0)[16:]) reset = ResetSignal(0, active=1, isasync=True) inst = fifo_2clock_cascade( wclk, datain, src_rdy_i, dst_rdy_o, space, rclk, dataout, src_rdy_o, dst_rdy_i, occupied, reset ) tb_convert(inst) clock = Signal(bool(0)) clear = Signal(bool(0)) inst = fifo_short( clock, reset, clear, datain, src_rdy_i, dst_rdy_o, dataout, src_rdy_o, dst_rdy_i ) tb_convert(inst)
def test_block_conversion(): """Test bench used for conversion purpose""" clock = Signal(bool(0)) reset = ResetSignal(0, active=True, async=True) dividend = Signal(intbv(0)[12:].signed()) divisor = Signal(intbv(0)[8:]) quotient = Signal(intbv(0)[12:].signed()) @block def bench_divider(): """Wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """Dummy tests to convert the module""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset verify.simulator = 'iverilog' assert bench_divider().verify_convert() == 0
def xula_vga( # ~~~[PORTS]~~~ vselect, hsync, vsync, red, green, blue, pxlen, active, clock, reset=None, # ~~~~[PARAMETERS]~~~~ # @todo: replace these parameters with a single VGATimingParameter resolution=(640, 480,), color_depth=(8, 8, 8,), refresh_rate=60, line_rate=31250 ): """ (arguments == ports) Arguments: vselect: Parameters: resolution: the video resolution color_depth: the color depth of a pixel, the number of bits for each color component in a pixel. refresh_rate: the refresh rate of the video """ # stub out reset if needed if reset is None: reset = ResetSignal(0, active=0, async=False) @always(clock.posedge) def reset_stub(): reset.next = not reset.active else: reset_stub = None # create the system-level signals, overwrite clock, reset glbl = Global(clock=clock, reset=reset) # VGA inteface vga = VGA() # assign the top-level ports to the VGA interface vga.assign( hsync=hsync, vsync=vsync, red=red, green=green, blue=blue, pxlen=pxlen, active=active ) # video memory interface vmem = VideoMemory(color_depth=color_depth) # color bar generation bar_inst = color_bars(glbl, vmem, resolution=resolution) # VGA driver vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution) return myhdl.instances()
def convert_to_verilog(): clk, load = [Signal(bool(0)) for i in range(2)] rst = ResetSignal(bool(0), active=0, isasync=True) par_in = Signal(intbv(0)[32:]) par_out = Signal(intbv(0)[32:]) inst = Register(clk, rst, load, par_in, par_out) inst.convert(name="DRegister_32Bit", hdl='Verilog')
def testbench(): mode = Signal(bool(0)) key = Signal(bool(0)) clk = Signal(bool(0)) reset = ResetSignal(1, active=ACTIVE_LOW, async=0) message = Signal() out = Signal() cezar_0 = cezar(mode, key, out, message, clk, reset) @always(delay(10)) def clkgen(): clk.next = not clk @instance def stimulus(): for i in range(3): yield clk.negedge for n in (12, 8, 8, 4): mode.next = 1 yield clk.negedge mode.next = 0 for i in range(n - 1): yield clk.negedge raise StopSimulation() return cezar_0, clkgen, stimulus
def test_name_conflict_after_replace(): clock = Signal(False) reset = ResetSignal(0, active=0, isasync=False) a = Intf() a_x = Signal(intbv(0)[len(a.x):]) inst = name_conflict_after_replace(clock, reset, a, a_x) assert inst.analyze_convert() == 0
def testbench(): m = 3 count = Signal(modbv(0)[m:]) enable = Signal(bool(0)) clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=True) inc_1 = inc(count, enable, clock, reset) HALF_PERIOD = delay(10) @always(HALF_PERIOD) def clockGen(): clock.next = not clock @instance def stimulus(): reset.next = ACTIVE_LOW yield clock.negedge reset.next = INACTIVE_HIGH for i in range(16): enable.next = min(1, randrange(3)) yield clock.negedge raise StopSimulation() @instance def monitor(): print("enable count") yield reset.posedge while 1: yield clock.posedge yield delay(1) print(" %s %s" % (int(enable), count)) return clockGen, stimulus, inc_1, monitor
def create_clock_reset_old(rst_value=True, rst_active=True, rst_async=False): print( "Warning: Don't use the ResetSignal as a precaution, the default values don't seem to work..." ) return Signal(False), ResetSignal(val=rst_value, active=rst_active, async=rst_async)
def test_block_conversion(): """ In the current test are tested the outputs of the converted testbench in verilog and VHDL with the outputs of the myhdl module """ samples, frac_bits, nbits = 50, 14, 8 pixel_bits, num_fractional_bits = nbits, frac_bits rgb, ycbcr = RGB(pixel_bits), YCbCr(pixel_bits) clock = Signal(bool(0)) reset = ResetSignal(1, active=True, async=True) in_out_data = InputsAndOutputs(samples) in_out_data.initialize() exp_y, exp_cb, exp_cr = in_out_data.get_rom_tables()[0] in_r, in_g, in_b = in_out_data.get_rom_tables()[1] y_s, cb_s, cr_s = [Signal(intbv(0)[pixel_bits:]) for _ in range(3)] @myhdl.block def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] if ycbcr.data_valid == 1: # expected_outputs signal assignment y_s.next = exp_y[i - 3] cb_s.next = exp_cb[i - 3] cr_s.next = exp_cr[i - 3] yield delay(1) print("Expected outputs ===>Y:%d Cb:%d Cr:%d" % (y_s, cb_s, cr_s)) print("Actual outputs ===>Y:%d Cb:%d Cr:%d" % (ycbcr.y, ycbcr.cb, ycbcr.cr)) print("----------------------------") yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim, tbrst assert bench_color_trans().verify_convert() == 0
def __init__(self, clkin): self.clkin = clkin self.rst = ResetSignal(True, True, True) # Memory data transfer clock period (ps) self.MEMCLK_PERIOD = 3000 self.DIVCLK_DIVIDE = 1 self.CLKFBOUT_MULT = 6 # 133 / 1 * 6 = 800 MHz self.CLKFBOUT_MULT = 5 # 133 / 1 * 5 = 666 MHz self.CLK_2X_DIVIDE = 1 self.FAST_CLK_DIVIDE = 20 self.MCB_UI_CLK_DIVIDE = 2 * self.CLKFBOUT_MULT self.SOC_CLK_DIVIDE = self.CLKFBOUT_MULT self.calib_done = Signal(False) self.fast_clk = Signal(False) self.fast_clk_locked = Signal(False) self.mcb_ui_clk = Signal(False) self.mcb_ui_clk_locked = Signal(False) self.soc_clk = Signal(False) self.soc_clk_b = Signal(False) self.soc_clk_locked = Signal(False) self.mcbx_dram_clk = Signal(False) self.mcbx_dram_clk_n = Signal(False) self.mcbx_dram_cke = '' self.mcbx_dram_ras_n = Signal(False) self.mcbx_dram_cas_n = Signal(False) self.mcbx_dram_we_n = Signal(False) self.mcbx_dram_ba = Signal(intbv(0)[2:]) self.mcbx_dram_addr = Signal(intbv(0)[13:]) self.mcbx_dram_dqs = Signal(False) self.mcbx_dram_dqs_n = Signal(False) self.mcbx_dram_udqs = Signal(False) self.mcbx_dram_udqs_n = Signal(False) self.mcbx_dram_udm = Signal(False) self.mcbx_dram_ldm = Signal(False) self.mcbx_dram_dq = Signal(intbv(0)[16:]) self.mcbx_dram_odt = '' self.mcbx_dram_ddr3_rst = '' self.mcbx_rzq = '' self.mcbx_zio = '' self.ports = [ None for _ in range(6) ]
def test_top_level_interfaces_analyze(): Clk = Signal(bool(0)) Reset = ResetSignal(0, 1, True) Table = TableXY() Position = Cartesian2D() dfc = XYTable(Clk, Reset, Table, Position) assert dfc.analyze_convert() == 0
def convert_gray_inc_reg(hdl, width=8): graycnt = Signal(modbv(0)[width:]) enable = Signal(bool()) clock = Signal(bool()) reset = ResetSignal(0, active=0, isasync=True) inst = gray_inc_reg(graycnt, enable, clock, reset, width) inst.convert(hdl)
def convert(): clock = Signal(bool(0)) reset = ResetSignal(0, 0, False) sdi = Signal(bool(0)) sdo = Signal(bool(0)) inst = serio_ex(clock, reset, sdi, sdo) inst.convert(hdl='Verilog', directory='output')
def test_three_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, isasync=True) x = Signal(intbv(3, min=-5000, max=5000)) y = Signal(intbv(4, min=-200, max=200)) intf = IntfWithConstant2() inst = top_const(clock, reset, x, y, intf) assert inst.analyze_convert() == 0
def convert_to_verilog(): en, clk, we = [Signal(bool(0)) for i in range(3)] rst = ResetSignal(bool(0), active=0, isasync=True) count = Signal(intbv(0)[12:]) w_in = Signal(intbv(0)[12:]) counter_1 = counter(clk, rst, en, we, count, w_in) counter_1.convert(hdl='Verilog')
def __init__(self, clk, val, active): self.clk = clk ResetSignal.__init__(self, val, active, async=False)