def test_generator():
testable_components = [
TestableComponent(source_file)
for source_file in TestableComponent.list_available()
]
nrn_components = [
tc() for tc in testable_components
] # if (tc.has_metadata() and tc.metadata.is_neuron_model)]
for tc in nrn_components:
yield write_and_compile_nmodl, tc
def main(src=None):
build_dir = 'build/'
output_dir = 'output/'
print 'Clearing output directory: %s' % output_dir
clear_and_recreate_dir(output_dir)
# single_file_mode = os.path.isfile(src)
if src:
print ' Testing Component: %s' % src
src_files = [src]
else:
print ' Testing all Components.'
src_files = TestableComponent.list_available()
# src_files = glob.glob( src + '/*.py')
for src_file in src_files:
# Clear the build-dir
clear_and_recreate_dir(build_dir)
clear_and_recreate_dir('nineml_mechanisms')
# Load the file:
print ' -- Loading from file: %s' % src_file
t = TestableComponent(src_file)
# Run some tests:
TestXMLWriteReadWrite.test(t, build_dir=build_dir)
TestWriteDot.test(t, build_dir=build_dir)
if t.has_metadata():
if t.metadata.is_neuron_model:
test_write_mod(t)
if src:
flg = 'supports_test_pynn_neuron_std'
if t.metadata.__dict__.get(flg, False):
test_pynn_neuron_std(t)
# Save all the output files:
shutil.move(build_dir, output_dir)
shutil.move(os.path.join(output_dir, build_dir),
os.path.join(output_dir, src_file.replace('.py', '')))
print ' Everything Ran Fine'
print ' -------------------'
def test_connect_ports(self):
# Signature: name(self, src, sink)
# Connects the ports of 2 subcomponents.
#
# The ports can be specified as ``string`` s or ``NamespaceAddresses`` es.
#
#
# :param src: The source port of one sub-component; this should either an
# event port or analog port, but it *must* be a send port.
#
# :param sink: The sink port of one sub-component; this should either an
# event port or analog port, but it *must* be either a 'recv' or a
# 'reduce' port.
tIaf = TestableComponent('iaf')
tCoba = TestableComponent('coba_synapse')
# Should be fine:
c = ComponentClass(name='C1',
subnodes={
'iaf': tIaf(),
'coba': tCoba()
})
c.connect_ports('iaf.V', 'coba.V')
c = ComponentClass(name='C1',
subnodes={
'iaf': tIaf(),
'coba': tCoba()
},
portconnections=[('iaf.V', 'coba.V')])
# Non existant Ports:
c = ComponentClass(name='C1',
subnodes={
'iaf': tIaf(),
'coba': tCoba()
})
self.assertRaises(NineMLRuntimeError, c.connect_ports, 'iaf.V1',
'coba.V')
self.assertRaises(NineMLRuntimeError, c.connect_ports, 'iaf.V',
'coba.V1')
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='C1',
subnodes={
'iaf': tIaf(),
'coba': tCoba()
},
portconnections=[('iaf.V1', 'coba.V')])
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='C1',
subnodes={
'iaf': tIaf(),
'coba': tCoba()
},
portconnections=[('iaf.V', 'coba.V1')])
# Connect ports the wronf way around:
# [Check the wright way around works:]
c = ComponentClass(name='C1',
subnodes={
'iaf': tIaf(),
'coba': tCoba()
},
portconnections=[('coba.I', 'iaf.ISyn')])
# And the wrong way around:
c = ComponentClass(name='C1',
subnodes={
'iaf': tIaf(),
'coba': tCoba()
})
self.assertRaises(NineMLRuntimeError, c.connect_ports, 'iaf.ISyn.',
'coba.I')
self.assertRaises(NineMLRuntimeError, c.connect_ports, 'coba.V',
'iaf.V')
# Error raised on duplicate port-connection:
c = ComponentClass(
name='C1',
subnodes={
'iaf': tIaf(),
'coba': tCoba()
},
)
c.connect_ports('coba.I', 'iaf.ISyn')
self.assertRaises(NineMLRuntimeError, c.connect_ports, 'coba.I',
'iaf.ISyn')
def test_generator():
testable_components = [TestableComponent(source_file)
for source_file in TestableComponent.list_available()]
nrn_components = [tc() for tc in testable_components] # if (tc.has_metadata() and tc.metadata.is_neuron_model)]
for tc in nrn_components:
yield write_and_compile_nmodl, tc
