def assemble_platform(): platform = ICEBreakerPlatform() i2s_conn = ('pmod', 0) seg7_conn = ('pmod', 1) i2s = Resource( 'i2s', 0, Subsignal('mclk', Pins('1', conn=i2s_conn, dir='o')), Subsignal('lrck', Pins('2', conn=i2s_conn, dir='o')), Subsignal('sck', Pins('3', conn=i2s_conn, dir='o')), Subsignal('sd', Pins('4', conn=i2s_conn, dir='o')), ) seg7 = Resource( 'seg7', 0, Subsignal('segs', Pins('1 2 3 4 7 8 9', conn=seg7_conn, dir='o')), Subsignal('digit', Pins('10', conn=seg7_conn, dir='o'))) midi = UARTResource(1, rx='39', tx='40', attrs=Attrs(IO_STANDARD='SB_LVCMOS')) dbg = Resource( 'dbg', 0, Subsignal('dbg', Pins('7 8 9 10', conn=i2s_conn, dir='o')), ) platform.add_resources((i2s, seg7, midi, dbg)) return platform
def buildAndRunTest(demo, resolution, seed, retime, program): from nmigen_boards.icebreaker import ICEBreakerPlatform platform = ICEBreakerPlatform() add_gpdi_resources(platform) synth_opts = ["-retime"] if retime else [] platform.build(demo(resolution), do_program=program, synth_opts=synth_opts, nextpnr_opts=["--seed", seed])
def assemble_platform(): platform = ICEBreakerPlatform() seg7_conn = ('pmod', 1) seg7 = Resource( 'seg7', 0, Subsignal('segs', Pins('1 2 3 4 7 8 9', conn=seg7_conn, dir='o')), Subsignal('digit', Pins('10', conn=seg7_conn, dir='o'))) midi = UARTResource(1, rx='39', tx='40', attrs=Attrs(IO_STANDARD='SB_LVCMOS')) platform.add_resources((seg7, midi)) return platform
def find_freq(experiment, seed): platform = ICEBreakerPlatform() platform.build(experiment, do_program=False, synth_opts=["-relut"], nextpnr_opts=[*"--placer heap --seed".split(), str(seed)]) # Return second clock output line found_once = False with open('build/top.tim') as f: for line in f: if r"Max frequency for clock 'cd_sync_clk12_0__i" in line: if found_once: m = re.search(r' ([0-9.]+) MHz', line) return float(m.group(1)) found_once = True
def get_platform() -> Platform: from nmigen_boards.icebreaker import ICEBreakerPlatform from amaranth.build.dsl import Resource, Pins, Attrs platform = ICEBreakerPlatform() # for IceBreaker board - comes from # https://github.com/icebreaker-fpga/icebreaker-migen-examples/blob/master/uart/uart.py # # The debug pins are on the PMOD1A in the following order on the connector: # 7 8 9 10 1 2 3 4 # Yes that means that the pins at the edge of the board come first # and the pins further away from the edge second platform.add_resources([ Resource("debug", 0, Pins("7 8 9 10 1 2 3 4", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")) ]) return platform
def build_and_program(pll_freq, sample_freq, depth): platform = ICEBreakerPlatform() platform.add_resources([ Resource( 'i2s', 0, Subsignal('mclk', Pins('1', conn=('pmod', 0), dir='o')), Subsignal('lrck', Pins('2', conn=('pmod', 0), dir='o')), Subsignal('sck', Pins('3', conn=('pmod', 0), dir='o')), Subsignal('sd', Pins('4', conn=('pmod', 0), dir='o')), ), ]) top = Top(pll_freq=pll_freq, sample_freq=sample_freq, depth=depth) platform.build(top, do_program=True) colorize = os.isatty(sys.stdout.fileno()) if colorize: print('\33[1;41m') print( f'Buzzer w/ PLL = {pll_freq / 1_000_000} MHz, ' f'samples = {depth} x {sample_freq:,}', end='') print('\33[m\n' if colorize else '', flush=True)
def p(): # depth >4 leads to use of memory (4k primitive, see build/top.rpt) top = Top(sim=False) platform = ICEBreakerPlatform() platform.build(top, do_program=True)
def out_proc(): seq = (0b00, 0b01, 0b11, 0b10) yield iq_to_step_dir.iq.eq(0b00) for _ in range(16): for _ in range(4): for iq in seq: yield iq_to_step_dir.iq.eq(iq) yield yield yield yield for _ in range(4): for iq in seq[::-1]: yield iq_to_step_dir.iq.eq(iq) yield yield yield yield sim.add_sync_process(out_proc) with sim.write_vcd("rotary_encoder.vcd", "rotary_encoder.gtkw", traces=[iq_to_step_dir.iq, iq_to_step_dir.step, iq_to_step_dir.direction]): sim.run() else: plat = ICEBreakerPlatform() plat.add_resources(plat.break_off_pmod) plat.add_resources(rotary_encoder_pmod) plat.build(Top(), do_program=True)
uart_pins = platform.request('uart') bad_led = platform.request('led', 0) good_led = platform.request('led', 1) digit_leds = [platform.request('led', i + 2) for i in range(5)] m = Module() uart_rx = UARTRx(divisor=uart_divisor) recv_status = OneShot(duration=status_duration) err_status = OneShot(duration=status_duration) m.submodules += [uart_rx, recv_status, err_status] m.d.comb += [ uart_rx.rx_pin.eq(uart_pins.rx), recv_status.i_trg.eq(uart_rx.rx_rdy), good_led.eq(recv_status.o_pulse), err_status.i_trg.eq(uart_rx.rx_err), bad_led.eq(err_status.o_pulse), ] with m.If(uart_rx.rx_rdy): m.d.sync += [ digit_leds[i].eq(uart_rx.rx_data == ord('1') + i) for i in range(5) ] return m if __name__ == '__main__': platform = ICEBreakerPlatform() platform.add_resources(platform.break_off_pmod) top = Top() platform.build(top, do_program=True)
] class Top(Elaboratable): def __init__(self): pass def elaborate(self, platform): bin_conv_ports = platform.request("bin_conv_ports") b2d = Bin2Dec(8) m = Module() m.submodules.bin2dec = b2d m.d.comb += [ b2d.i_bin.eq(bin_conv_ports.bin_value), b2d.i_bin_stb.eq(bin_conv_ports.bin_stb), bin_conv_ports.dec_digit.eq(b2d.o_digit), bin_conv_ports.digit_rd.eq(b2d.o_digit_rd), bin_conv_ports.conv_rd.eq(b2d.o_conv_rd), ] return m if __name__ == '__main__': platform = ICEBreakerPlatform() platform.add_resources(bin_conv_resources) platform.build(Top(), do_program=True)
uart_rx.rx_pin.eq(uart_pins.rx), recv_status.trg.eq(uart_rx.rx_rdy), good_led.eq(recv_status.out), err_status.trg.eq(uart_rx.rx_err), bad_led.eq(err_status.out), ones_segs.digit_in.eq(uart_rx.rx_data[:4]), tens_segs.digit_in.eq(uart_rx.rx_data[4:]), driver.segment_patterns[0].eq(ones_segs.segments_out), driver.segment_patterns[1].eq(tens_segs.segments_out), seg7_pins.eq(driver.seg7), ] m.d.sync += [ driver.pwm.eq(driver.pwm | uart_rx.rx_rdy), ] return m if __name__ == '__main__': platform = ICEBreakerPlatform() conn = ('pmod', 1) platform.add_resources([ Resource( 'seg7', 0, Subsignal('segs', Pins('1 2 3 4 7 8 9', conn=conn, dir='o')), Subsignal('digit', Pins('10', conn=conn, dir='o')), ), ]) top = Top() platform.build(top, do_program=True)
self.leds = leds def elaborate(self, _platform: Platform) -> Module: m = Module() # Timer m.d.comb += self.period.eq(self.maxperiod) with m.If(self.counter == 0): m.d.sync += [ self.state_counter.eq(self.state_counter + 1), self.counter.eq(self.period) ] with m.Else(): m.d.sync += self.counter.eq(self.counter - 1) # LEDs m.d.comb += self.leds.oe.eq(~self.state_counter[0]) for i in range(len(self.leds.o)): m.d.comb += self.leds.o[i].eq(self.state_counter[1]) return m if __name__ == "__main__": plat = ICEBreakerPlatform() plat.add_resources(triled_pmod) leds = plat.request("triled") my_blinker = Blinker(leds, 10000000) plan = plat.build(my_blinker, do_program=True)
m.d.comb += [ vga_pads.red.eq(still.red), vga_pads.green.eq(still.green), vga_pads.blue.eq(still.blue), ] with m.Else(): m.d.comb += [ vga_pads.red.eq(test_pattern.red), vga_pads.green.eq(test_pattern.green), vga_pads.blue.eq(test_pattern.blue), ] m.submodules.uart = uart = UARTLoopback( uart_pads, clk_freq=12e6, baud_rate=115200, ) m.d.comb += [ leds.eq(uart.rx_data[0:2]), ] return m if __name__ == '__main__': top = PixtolicTop(color_depth=4) platform = ICEBreakerPlatform() platform.add_resources(vga_pmod) products = platform.build(top, do_build=True, do_program=False) platform.toolchain_program(products, 'top')
#!/usr/bin/env nmigen from nmigen import * from nmigen_boards.icebreaker import ICEBreakerPlatform from nmigen_lib.blinker import Blinker class Top(Elaboratable): def elaborate(self, platform): led = platform.request('user_led') m = Module() bink = Blinker(period=int(platform.default_clk_frequency)) m.submodules += bink m.d.comb += led.eq(bink.led) return m if __name__ == '__main__': platform = ICEBreakerPlatform() platform.build(Top(), do_program=True)
pll = PLL(freq_in_mhz=freq_in_mhz, freq_out_mhz=pll_freq_mhz) i2s = I2SOut(pll_freq) buzzer = Buzzer(buzz_freq, i2s.sample_frequency) m.domains += pll.domain # override the default 'sync' domain m.submodules += [pll, buzzer, i2s] m.d.comb += [ pll.clk_pin.eq(clk_pin), buzzer.enable.eq(True), buzzer.ack.eq(i2s.ack), i2s.samples[0].eq(buzzer.sample), i2s.samples[1].eq(buzzer.sample), i2s.stb.eq(buzzer.stb), i2s_pins.eq(i2s.i2s), ] return m if __name__ == '__main__': platform = ICEBreakerPlatform() platform.add_resources([ Resource( 'i2s', 0, Subsignal('mclk', Pins('1', conn=('pmod', 0), dir='o')), Subsignal('lrck', Pins('2', conn=('pmod', 0), dir='o')), Subsignal('sck', Pins('3', conn=('pmod', 0), dir='o')), Subsignal('sd', Pins('4', conn=('pmod', 0), dir='o')), ), ]) platform.build(Top(), do_program=True)
def g(): top = Top(sim=False) platform = ICEBreakerPlatform() print(verilog.convert(top, ports=[], platform=platform))
yield r.wren.eq(1) yield yield def process(): yield from write(0x0010, 0x1111) yield from read(0x0010) self.assertEqual(0x1111, (yield r.data_out)) yield from write(0x4010, 0x2222) yield from read(0x4010) self.assertEqual(0x2222, (yield r.data_out)) yield from write(0xc010, 0xffff) yield from read(0xc010) self.assertEqual(0xffff, (yield r.data_out)) yield from read(0x0010) self.assertEqual(0x1111, (yield r.data_out)) self.run_sim(process) if __name__ == '__main__': parser = argparse.ArgumentParser() parser.add_argument('-g', '--generate', action='store_true', help='Generate Verilog for oscilator') args = parser.parse_args() if args.generate: from nmigen_boards.icebreaker import ICEBreakerPlatform print(verilog.convert(SinglePortRam(), platform=ICEBreakerPlatform())) else: unittest.main()
] return m if __name__ == "__main__": parser = argparse.ArgumentParser() parser.add_argument("-s", action="store_true", help="Simulate PDMDriver (for debugging).") parser.add_argument("-g", type=float, default=2.2, help="Gamma exponent (default 2.2)") args = parser.parse_args() if args.s: p = PDMDriver(8) sim = pysim.Simulator(p) sim.add_clock(1.0 / 12e6) def out_proc(): for i in range(256): yield p.pdm_in.eq(i) yield yield yield yield sim.add_sync_process(out_proc) with sim.write_vcd("drv.vcd", "drv.gtkw", traces=[p.pdm_in, p.pdm_out]): sim.run() else: plat = ICEBreakerPlatform() plat.build(Top(gamma=args.g), do_program=True)
def p(): # depth >4 leads to use of memory (4k primitive, see build/top.rpt) top = Top(sim=False, sim_tx_cycle_accurate=False, xwidth=xwidth, nwidth=nwidth) platform = ICEBreakerPlatform() platform.build(top, do_program=True)
Subsignal('act', Pins('9', conn=pmod1, dir='o')), Subsignal('clk', Pins('2', conn=pmod1, dir='o')), ), ]) if __name__ == '__main__': parser = argparse.ArgumentParser() parser.add_argument('-g', '--generate', action='store_true', help='Generate Verilog for output') args = parser.parse_args() if args.generate: platform = ICEBreakerPlatform() add_gpdi_resources(platform) class Top(Elaboratable): def elaborate(self, plat): gpdi = platform.request('gpdi') m = Module() rgb = RGB() vt = VT() go = GPDIOutput(gpdi, rgb, vt) m.submodules += [rgb, vt, go] return m class VT(Elaboratable): def __init__(self): self.frame_start = Signal(
def g(): top = Top(sim=False, sim_tx_cycle_accurate=False, xwidth=xwidth, nwidth=nwidth) platform = ICEBreakerPlatform() print(verilog.convert(top, ports=[top.tx, top.rx], platform=platform))
m = Module() # Rx signals are input, have to read always from Rx and write to Tx. # uart Rx -> ext Tx # ext Rx -> uart Tx m.d.comb += [ ext_pins.tx.eq(uart_pins.rx), uart_pins.tx.eq(ext_pins.rx), ] return m if __name__ == '__main__': plat = ICEBreakerPlatform() plat.add_resources(plat.break_off_pmod) # The external IO pins to use ext_io = [ Resource( 'ext_io', 0, # External Input Subsignal('rx', Pins('4', dir='i', conn=('pmod', 0)), Attrs(IO_STANDARD="LVCMOS33", PULLUP=1)), # External Output Subsignal('tx', Pins('3', dir='o', conn=('pmod', 0)), Attrs(IO_STANDARD="LVCMOS33", PULLUP=1)), ), ]
def elaborate(self, _platform): m = Module() with m.Switch(self.digit): for n, seg_val in enumerate([ 0b0111111, 0b0000110, 0b1011011, 0b1001111, 0b1100110, 0b1101101, 0b1111101, 0b0000111, 0b1111111, 0b1101111, 0b1110111, 0b1111100, 0b0111001, 0b1011110, 0b1111001, 0b1110001 ]): with m.Case(n): m.d.sync += self.segments.eq(seg_val) return m if __name__ == "__main__": # In this example, explicitly show the intermediate classes used to # execute build() to demonstrate that a user can inspect # each part of the build process (create files, execute, program, # and create a zip file if you have a BuildPlan instance). plat = ICEBreakerPlatform() plat.add_resources(seven_seg_pmod) # BuildPlan if do_build=False # BuildProducts if do_build=True and do_program=False # None otherwise. plan = plat.build(Top(), do_build=False, do_program=False) # BuildPlan products = plan.execute() # BuildProducts plat.toolchain_program(products, "top") # Manally run the programmer.