Exemple #1
0
        # xdr clock high => red led on
        m.d.comb += rgb_led.r.o.eq(ClockSignal("xdr"))

        if io_dir in ("oe", "io"):
            m.d.comb += led.oe.eq(0)

        if xdr == 0 or xdr == 1:
            # Connect button input straight to the green led
            m.d.comb += rgb_led.g.o.eq(btn.i)
        elif xdr == 2:
            # Rising edge  => green
            # Falling edge => blue
            m.d.comb += rgb_led.g.o.eq(btn.i0)
            m.d.comb += rgb_led.b.o.eq(btn.i1)

        return m

if __name__ == "__main__":
    p = TangNanoPlatform()
    # p.build(BlinkyXDROut(xdr=0), do_program=True)
    # p.build(BlinkyXDROut(xdr=1), do_program=True)
    # p.build(BlinkyXDROut(xdr=2), do_program=True)

    # p.build(BlinkyXDR10Out(), do_program=True)

    # p.build(BlinkyXDRIn(xdr=0), do_program=True)
    # p.build(BlinkyXDRIn(xdr=1), do_program=True)
    p.build(BlinkyXDRIn(xdr=2), do_program=True)

Exemple #2
0
from nmigen import *
from nmigen.build import *

from nmigen_boards.tang_nano import TangNanoPlatform

class Blinky(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        led = platform.request("rgb_led")

        clk_freq = platform.default_clk_frequency
        led_counter = Signal(range(int(clk_freq//2)), reset=int(clk_freq//2) - 1)

        with m.If(led_counter == 0):
            m.d.sync += led_counter.eq(led_counter.reset)
            m.d.sync += led.r.o.eq(~led.r.o)
        with m.Else():
            m.d.sync += led_counter.eq(led_counter - 1)

        return m

if __name__ == "__main__":
    p = TangNanoPlatform()
    p.build(Blinky(), do_program=True)
Exemple #3
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        m = Module()

        m.submodules.uart = uart = UART(
            divisor=round(platform.default_clk_frequency / self.baudrate),
            stopbits=self.stopbits
        )

        m.d.comb += uart.rx_i.eq(uart_pins.rx)
        m.d.comb += uart_pins.tx.eq(uart.tx_o)

        m.d.comb += led.eq(uart.rx_data[0])

        with m.If(~uart.rx_err & uart.rx_rdy & ~uart.rx_ack):
            m.d.sync += [
                uart.tx_rdy.eq(1),
                uart.tx_data.eq(uart.rx_data),
                uart.rx_ack.eq(1)
            ]
        with m.Elif(uart.tx_ack):
            m.d.sync += uart.tx_rdy.eq(0)
            m.d.sync += uart.rx_rdy.eq(0)
            m.d.sync += uart.rx_ack.eq(0)

        return m


if __name__ == "__main__":
    p = TangNanoPlatform()
    p.build(UARTExample(115200, 1), do_program=True)
Exemple #4
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        m.submodules.vga = VGAOutputSubtarget(vga_output, vga_parameters)

        r = Signal(8)
        g = Signal(8)
        b = Signal(8)
        m.submodules.imagegen = TestImageGenerator(
            vsync=vga_output.vs,
            h_ctr=m.submodules.vga.h_ctr,
            v_ctr=m.submodules.vga.v_ctr,
            r=r,
            g=g,
            b=b,
            speed=0)

        m.d.comb += [
            lcd.den.eq(~vga_output.blank),
            lcd.pclk.eq(ClockSignal()),
            lcd.hs.eq(vga_output.hs),
            lcd.vs.eq(vga_output.vs),
            lcd.r.eq(r[-5:]),
            lcd.g.eq(g[-6:]),
            lcd.b.eq(b[-5:]),
        ]

        return m


if __name__ == "__main__":
    p = TangNanoPlatform()
    p.build(LCDExample(), do_program=True)