def test_find_rtl_file_location(self):
        """give a filename that should be in the RTL"""
        result = utils.find_rtl_file_location("wb_gpio.v", debug=False)
        #print "file location: " + result
        try:
            testfile = open(result)
            result = True
            testfile.close()
        except:
            result = False

        self.assertEqual(result, True)
    def test_find_rtl_file_location(self):
        """give a filename that should be in the RTL"""
        result = utils.find_rtl_file_location("wb_gpio.v", debug=False)
        #print "file location: " + result
        try:
            testfile = open(result)
            result = True
            testfile.close()
        except:
            result = False

        self.assertEqual(result, True)
    def test_find_rtl_file_location_user_cbuilder(self):
        """give a filename that should be in the RTL"""
        loc = os.path.join(os.path.dirname(__file__), os.pardir, "fake")
        search_location = os.path.abspath(os.path.expanduser(loc))

        result = utils.find_rtl_file_location("test.v", [search_location],
                                              debug=False)
        #print "file location: " + result
        try:
            testfile = open(result)
            result = True
            testfile.close()
        except:
            result = False

        self.assertEqual(result, True)
Exemple #4
0
    def add_box(self, box_type, color, name, ID, position, rect=QRect()):
        """Add a box to the canvas"""
        scene = self.canvas.scene()
        if box_type == BoxType.SLAVE:
            fn = utils.find_module_filename(name, utils.get_local_verilog_paths())
            fn = utils.find_rtl_file_location(fn, utils.get_local_verilog_paths())

        if self.model is None:
            raise DesignControlError("Bus type is not set up corretly," +
                                     "please select either axi or bus")
        #self.model.add_slave
        return Box(position=position,
                   scene=scene,
                   name=name,
                   color=color,
                   select_func=self.box_select,
                   deselect_func=self.box_deselect,
                   user_data=ID)
    def test_find_rtl_file_location_user_cbuilder(self):
        """give a filename that should be in the RTL"""
        loc = os.path.join(os.path.dirname(__file__),
                           os.pardir,
                           "fake")
        search_location = os.path.abspath(os.path.expanduser(loc))

        result = utils.find_rtl_file_location(  "test.v",
                                            [search_location],
                                            debug=False)
        #print "file location: " + result
        try:
            testfile = open(result)
            result = True
            testfile.close()
        except:
            result = False

        self.assertEqual(result, True)
    def setup_host_interface(self):
        #Host interface is always present, if there is a user configuration
        #Associated with it, set all the appropriate values
        #print "setup host interface: %s" % (self.config_dict["PROJECT_NAME"])
        if "INTERFACE" not in self.config_dict:
            print "Interface is not in project tags"
            return
        project_tags = self.config_dict["INTERFACE"]
        self.set_node_project_tags(HOST_INTERFACE, project_tags)

        module_tags = {}

        if "filename" in project_tags:
            filename = project_tags["filename"]
            try:
                filepath = utils.find_rtl_file_location(filename, self.paths)
                module_tags = vutils.get_module_tags(filepath)
            except:
                print "%s: Could not  find Host Interface for file: %s" % (__file__, filename)

        self.set_node_module_tags(HOST_INTERFACE, module_tags)
        self.update_node_ports(HOST_INTERFACE)
        if "bind" in project_tags:
            self.set_node_bindings(HOST_INTERFACE, cu.expand_user_constraints(project_tags["bind"]))
Exemple #7
0
    def gen_som(self, tags = {}, buf = "", user_paths = [], debug = False):
        tags = copy.deepcopy(tags)
        self.rom_element_count = 0
        if "MEMORY" not in tags:
            tags["MEMORY"] = {}

        self.user_paths = user_paths
        board_name = tags["board"].lower()

        if not utils.board_exists(board_name):
            try:
                utils.install_remote_board_package(board_name)
            except IBuilderError as e:
                raise IBuilderError(                                            \
                                "Board %s could not be found, Attempted to "    \
                                "find it in the remote table and failed. If "   \
                                "this is a local board make sure to run the "   \
                                "local install" % (board_name))
                
        image_id = 0
        for key in tags.keys():
            if key.lower() == "image_id":
                image_id = tags[key]

        sm = som.SOM()
        sm.initialize_root()
        root = sm.get_root()
        #Add 1 for Root
        self.rom_element_count += 1

        peripheral = sm.insert_bus(root,
                                    name = "peripheral")
        memory = sm.insert_bus(     root,
                                    name = "memory")

        #Add one for SDB ROM
        self.rom_element_count += 1
        self.rom_element_count += 1
        version_major = device_manager.get_device_id_from_name("SDB")
        sdb_rom = sdbc.create_device_record(name = "SDB",
                                            version_major = version_major)

        #Add two for bridge and one extra for empty
        self.rom_element_count += 3

        #Peripheral Bus
        #Add one for interconnect
        self.rom_element_count += 1



        '''
        #Move all the platform peripherals to the front of the SDB Bus
        temp_unordered_platform_tags = {}
        temp_platform_tags = OrderedDict()
        temp_periph_tags = OrderedDict()
        minor_dict = {}
        peripheral_id = device_manager.get_device_id_from_name("platform")

        for key in tags["SLAVES"]:
            filename = tags["SLAVES"][key]["filename"]
            absfilename = utils.find_rtl_file_location(filename, self.user_paths)
            f = open(absfilename, 'r')
            slave_buffer = f.read()
            f.close()

            per = sdbc.create_device_record(name = key)
            per.parse_buffer(slave_buffer)

            if per.get_abi_version_major_as_int() == peripheral_id:
                minor = per.get_abi_version_minor_as_int()
                minor_dict[minor] = key
                temp_unordered_platform_tags[key] = tags["SLAVES"][key]
            else:
                temp_periph_tags[key] = tags["SLAVES"][key]

        if len(minor_dict.keys()) > 0:
            #Order the platforms in terms of their minor numbers
            ordered_keys = sorted(minor_dict.keys(), key=int)
            for okey in ordered_keys:
                key = minor_dict[okey]
                temp_platform_tags[key] = temp_unordered_platform_tags[key]
            
            #Add all the peripheral slaves
            for key in temp_periph_tags:
                temp_platform_tags[key] = temp_periph_tags[key]
            
            #Put the slaves back in the original dictionary
            tags["SLAVES"] = temp_platform_tags
        '''


        #Add one per peripheral
        for i in range (0, len(tags["SLAVES"])):
            key = tags["SLAVES"].keys()[i]

            if is_integration_required(tags["SLAVES"][key]):
                ir = generate_integration_record(tags["SLAVES"], key)
                #print "Inserting Integration record for: %s" % key
                sm.insert_component(peripheral, ir)

            filename = tags["SLAVES"][key]["filename"]
            absfilename = utils.find_rtl_file_location(filename, self.user_paths)
            f = open(absfilename, 'r')
            slave_buffer = f.read()
            f.close()

            per = sdbc.create_device_record(name = key)
            per.parse_buffer(slave_buffer)
            per.set_name(str(key))
            sm.insert_component(peripheral, per)
            self.rom_element_count += 1

        #Add one for empty
        self.rom_element_count += 1

        #Memory Bus
        #Add one for interconnect
        self.rom_element_count += 1

        #Add one per memory peripheral
        for i in range (0, len(tags["MEMORY"])):
            key = tags["MEMORY"].keys()[i]
            name = tags["MEMORY"][key]["filename"]
            absfilename = utils.find_rtl_file_location(name, self.user_paths)
            f = open(absfilename, 'r')
            memory_buffer = f.read()
            f.close()

            mem = sdbc.create_device_record(name = key)
            mem.parse_buffer(memory_buffer)
            mem.set_name(str(key))
            sm.insert_component(memory, mem)
            self.rom_element_count += 1

        #add one for empty
        self.rom_element_count += 1

        #TODO: add Add one for URL of repo ?? Maybe
        #TODO: add Add one for Synthesis Record
        self.rom_element_count += 1

        sdb_rom.set_size(self.rom_element_count * sdbc.SDB_ROM_RECORD_LENGTH)
        sm.insert_component(peripheral, sdb_rom, 0)

        #Generate the ROM image
        sm.set_child_spacing(root,       0x0100000000)
        sm.set_child_spacing(peripheral, 0x0001000000)
        return sm
def generate_wb_mem_interconnect(tags = {}, user_paths = [], debug = False):

  if "MEMORY" not in tags:
    return ""

  num_slaves = len(tags["MEMORY"].keys())
  if debug: print "Number of slaves: %d" % num_slaves


  buf = ""

  #Allow errors to pass up to the calling class
  directory = utils.get_local_verilog_path("nysa-verilog")
  wb_i_loc = os.path.join(  directory,
                            "verilog",
                            "wishbone",
                            "interconnect",
                            "wishbone_mem_interconnect.v")

  f = open(wb_i_loc, "r")
  buf = f.read()
  f.close()

  template = Template(buf)

  port_buf = ""
  port_def_buf = ""
  mem_select_buf = ""
  assign_buf = ""
  data_block_buf = ""
  ack_block_buf = ""
  int_block_buf = ""
  param_buf = ""

  #start with 1 to account for SDB
  num_mems = 0
  if (tags.has_key("MEMORY")):
    #got a list of all the slaves to add to make room for
    mem_list = tags["MEMORY"]
    num_mems = num_mems + len(mem_list)

  if num_mems == 0:
    return ""

  if debug:
    "Memory Keys\n\n"
    for key in tags["MEMORY"]:
      print key + ":" + str(tags["MEMORY"][key])
      print "\n\n"

  slave_keywords = [
      "SDB_ABI_VERSION_MAJOR",
      "SDB_ABI_VERSION_MINOR",
      "SDB_SIZE"
  ]

  mem_offset = 0
  #generate the parameters
  for i in range(0, num_mems):
    key = tags["MEMORY"].keys()[i]
    absfilename = utils.find_rtl_file_location(tags["MEMORY"][key]["filename"], user_paths)
    #print "filename: %s" % absfilename
    slave_tags = vutils.get_module_tags(filename = absfilename,
                                        bus = "wishbone",
                                        keywords = slave_keywords,
                                        project_tags = tags)
    if debug:
        print "slave tags: " + str(slave_tags)

    mem_size = int(slave_tags["keywords"]["SDB_SIZE"].strip(), 0)

    param_buf = param_buf + "parameter MEM_SEL_%d\t=\t%d;\n" % (i, i)
    #param_buf = param_buf + "parameter MEM_OFFSET_%d\t=\t %d;\n" % (i, mem_offset)
    param_buf = param_buf + "parameter MEM_OFFSET_%d\t=\t 32'h%08X;\n" % (i, mem_offset)
    param_buf = param_buf + "parameter MEM_SIZE_%d\t=\t 32'h%02X;\n" % (i, mem_size)
    mem_offset += mem_size

  #generate the memory select logic
  mem_select_buf =  "reg [31:0] mem_select;\n"

  mem_select_buf += "\n"
  mem_select_buf += "always @(rst or i_m_adr or mem_select) begin\n"
  mem_select_buf += "\tif (rst) begin\n"
  mem_select_buf += "\t\t//nothing selected\n"
  mem_select_buf += "\t\tmem_select <= 32'hFFFFFFFF;\n"
  mem_select_buf += "\tend\n"
  mem_select_buf += "\telse begin\n"
  for i in range (num_mems):
    if (i == 0):
      mem_select_buf += "\t\tif "
    else:
      mem_select_buf += "\t\telse if "

    mem_select_buf += "((i_m_adr >= MEM_OFFSET_%d) && (i_m_adr < (MEM_OFFSET_%d + MEM_SIZE_%d))) begin\n" % (i, i, i)
    mem_select_buf += "\t\t\tmem_select <= MEM_SEL_%d;\n" % i
    mem_select_buf += "\t\tend\n"

  mem_select_buf += "\t\telse begin\n"
  mem_select_buf += "\t\t\tmem_select <= 32'hFFFFFFFF;\n"
  mem_select_buf += "\t\tend\n"
  mem_select_buf += "\tend\n"
  mem_select_buf += "end\n"

  #Ports
  for i in range (0, num_slaves):
    port_buf += "\t//Slave %d\n" % i
    port_buf += "\toutput\t\t\t\t\t\t\to_s%d_we,\n" % i
    port_buf += "\toutput\t\t\t\t\t\t\to_s%d_cyc,\n" % i
    port_buf += "\toutput\t\t\t\t\t\t\to_s%d_stb,\n" % i
    port_buf += "\toutput\t\t[3:0]\t\t\to_s%d_sel,\n" % i
    port_buf += "\tinput\t\t\t\t\t\t\t\ti_s%d_ack,\n" % i
    port_buf += "\toutput\t\t[31:0]\t\to_s%d_dat,\n" % i
    port_buf += "\tinput\t\t\t[31:0]\t\ti_s%d_dat,\n" % i
    port_buf += "\toutput\t\t[31:0]\t\to_s%d_adr,\n" % i
    port_buf += "\tinput\t\t\t\t\t\t\t\ti_s%d_int" % i

    #if this isn't the last slave add a comma
    if (i < num_slaves - 1):
      port_buf += ",\n"

    port_buf += "\n"

  #assign defines
  for i in range (0, num_mems):
    assign_buf += "assign o_s%d_we   =\t(mem_select == MEM_SEL_%d) ? i_m_we: 1'b0;\n" % (i, i)
    assign_buf += "assign o_s%d_stb  =\t(mem_select == MEM_SEL_%d) ? i_m_stb: 1'b0;\n" % (i, i)
    assign_buf += "assign o_s%d_sel  =\t(mem_select == MEM_SEL_%d) ? i_m_sel: 4'b0;\n" % (i, i)
    assign_buf += "assign o_s%d_cyc  =\t(mem_select == MEM_SEL_%d) ? i_m_cyc: 1'b0;\n" % (i, i)
    if i == 0:
        assign_buf += "assign o_s%d_adr  =\t(mem_select == MEM_SEL_%d) ? i_m_adr: 32'h0;\n" % (i, i)
    else:
        assign_buf += "assign o_s%d_adr  =\t(mem_select == MEM_SEL_%d) ? i_m_adr - MEM_OFFSET_%d: 32'h0;\n" %(i, i, i)
    assign_buf += "assign o_s%d_dat  =\t(mem_select == MEM_SEL_%d) ? i_m_dat: 32'h0;\n" % (i, i)
    assign_buf +="\n"

  #data in block
  data_block_buf = "//data in from slave\n"
  data_block_buf += "always @ (mem_select"
  for i in range (0, num_mems):
    data_block_buf += " or i_s%d_dat" % i

  data_block_buf += ") begin\n\tcase (mem_select)\n"
  for i in range (0, num_mems):
    data_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_dat <= i_s%d_dat;\n\t\tend\n" % (i, i)
  data_block_buf += "\t\tdefault: begin\n\t\t\to_m_dat <= 32\'h0000;\n\t\tend\n\tendcase\nend\n\n"

  #ack in block
  ack_block_buf = "//ack in from mem slave\n"
  ack_block_buf += "always @ (mem_select"
  for i in range (0, num_mems):
    ack_block_buf += " or i_s%d_ack" % i
  ack_block_buf += ") begin\n\tcase (mem_select)\n"
  for i in range (0, num_mems):
    ack_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_ack <= i_s%d_ack;\n\t\tend\n" % (i, i)
  ack_block_buf += "\t\tdefault: begin\n\t\t\to_m_ack <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"

  #int in block
  int_block_buf = "//int in from slave\n"
  int_block_buf += "always @ (mem_select"
  for i in range (0, num_mems):
    int_block_buf += " or i_s%d_int" % (i)
  int_block_buf += ") begin\n\tcase (mem_select)\n"
  for i in range (0, num_mems):
    int_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_int <= i_s%d_int;\n\t\tend\n" % (i, i)
  int_block_buf += "\t\tdefault: begin\n\t\t\to_m_int <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"

  buf = template.substitute(  PORTS=port_buf,
                MEM_SELECT=mem_select_buf,
                ASSIGN=assign_buf,
                DATA=data_block_buf,
                ACK=ack_block_buf,
                INT=int_block_buf,
                MEM_PARAMS=param_buf)
  buf = string.expandtabs(buf, 2)

  return buf
Exemple #9
0
def generate_wb_mem_interconnect(tags={}, user_paths=[], debug=False):

    if "MEMORY" not in tags:
        return ""

    num_slaves = len(tags["MEMORY"].keys())
    if debug: print "Number of slaves: %d" % num_slaves

    buf = ""

    #Allow errors to pass up to the calling class
    directory = utils.get_local_verilog_path("nysa-verilog")
    wb_i_loc = os.path.join(directory, "verilog", "wishbone", "interconnect",
                            "wishbone_mem_interconnect.v")

    f = open(wb_i_loc, "r")
    buf = f.read()
    f.close()

    template = Template(buf)

    port_buf = ""
    port_def_buf = ""
    mem_select_buf = ""
    assign_buf = ""
    data_block_buf = ""
    ack_block_buf = ""
    int_block_buf = ""
    param_buf = ""

    #start with 1 to account for SDB
    num_mems = 0
    if (tags.has_key("MEMORY")):
        #got a list of all the slaves to add to make room for
        mem_list = tags["MEMORY"]
        num_mems = num_mems + len(mem_list)

    if num_mems == 0:
        return ""

    if debug:
        "Memory Keys\n\n"
        for key in tags["MEMORY"]:
            print key + ":" + str(tags["MEMORY"][key])
            print "\n\n"

    slave_keywords = [
        "SDB_ABI_VERSION_MAJOR", "SDB_ABI_VERSION_MINOR", "SDB_SIZE"
    ]

    mem_offset = 0
    #generate the parameters
    for i in range(0, num_mems):
        key = tags["MEMORY"].keys()[i]
        absfilename = utils.find_rtl_file_location(
            tags["MEMORY"][key]["filename"], user_paths)
        #print "filename: %s" % absfilename
        slave_tags = vutils.get_module_tags(filename=absfilename,
                                            bus="wishbone",
                                            keywords=slave_keywords,
                                            project_tags=tags)
        if debug:
            print "slave tags: " + str(slave_tags)

        mem_size = int(slave_tags["keywords"]["SDB_SIZE"].strip(), 0)

        param_buf = param_buf + "parameter MEM_SEL_%d\t=\t%d;\n" % (i, i)
        #param_buf = param_buf + "parameter MEM_OFFSET_%d\t=\t %d;\n" % (i, mem_offset)
        param_buf = param_buf + "parameter MEM_OFFSET_%d\t=\t 32'h%08X;\n" % (
            i, mem_offset)
        param_buf = param_buf + "parameter MEM_SIZE_%d\t=\t 32'h%02X;\n" % (
            i, mem_size)
        mem_offset += mem_size

    #generate the memory select logic
    mem_select_buf = "reg [31:0] mem_select;\n"

    mem_select_buf += "\n"
    mem_select_buf += "always @(rst or i_m_adr or mem_select) begin\n"
    mem_select_buf += "\tif (rst) begin\n"
    mem_select_buf += "\t\t//nothing selected\n"
    mem_select_buf += "\t\tmem_select <= 32'hFFFFFFFF;\n"
    mem_select_buf += "\tend\n"
    mem_select_buf += "\telse begin\n"
    for i in range(num_mems):
        if (i == 0):
            mem_select_buf += "\t\tif "
        else:
            mem_select_buf += "\t\telse if "

        mem_select_buf += "((i_m_adr >= MEM_OFFSET_%d) && (i_m_adr < (MEM_OFFSET_%d + MEM_SIZE_%d))) begin\n" % (
            i, i, i)
        mem_select_buf += "\t\t\tmem_select <= MEM_SEL_%d;\n" % i
        mem_select_buf += "\t\tend\n"

    mem_select_buf += "\t\telse begin\n"
    mem_select_buf += "\t\t\tmem_select <= 32'hFFFFFFFF;\n"
    mem_select_buf += "\t\tend\n"
    mem_select_buf += "\tend\n"
    mem_select_buf += "end\n"

    #Ports
    for i in range(0, num_slaves):
        port_buf += "\t//Slave %d\n" % i
        port_buf += "\toutput\t\t\t\t\t\t\to_s%d_we,\n" % i
        port_buf += "\toutput\t\t\t\t\t\t\to_s%d_cyc,\n" % i
        port_buf += "\toutput\t\t\t\t\t\t\to_s%d_stb,\n" % i
        port_buf += "\toutput\t\t[3:0]\t\t\to_s%d_sel,\n" % i
        port_buf += "\tinput\t\t\t\t\t\t\t\ti_s%d_ack,\n" % i
        port_buf += "\toutput\t\t[31:0]\t\to_s%d_dat,\n" % i
        port_buf += "\tinput\t\t\t[31:0]\t\ti_s%d_dat,\n" % i
        port_buf += "\toutput\t\t[31:0]\t\to_s%d_adr,\n" % i
        port_buf += "\tinput\t\t\t\t\t\t\t\ti_s%d_int" % i

        #if this isn't the last slave add a comma
        if (i < num_slaves - 1):
            port_buf += ",\n"

        port_buf += "\n"

    #assign defines
    for i in range(0, num_mems):
        assign_buf += "assign o_s%d_we   =\t(mem_select == MEM_SEL_%d) ? i_m_we: 1'b0;\n" % (
            i, i)
        assign_buf += "assign o_s%d_stb  =\t(mem_select == MEM_SEL_%d) ? i_m_stb: 1'b0;\n" % (
            i, i)
        assign_buf += "assign o_s%d_sel  =\t(mem_select == MEM_SEL_%d) ? i_m_sel: 4'b0;\n" % (
            i, i)
        assign_buf += "assign o_s%d_cyc  =\t(mem_select == MEM_SEL_%d) ? i_m_cyc: 1'b0;\n" % (
            i, i)
        if i == 0:
            assign_buf += "assign o_s%d_adr  =\t(mem_select == MEM_SEL_%d) ? i_m_adr: 32'h0;\n" % (
                i, i)
        else:
            assign_buf += "assign o_s%d_adr  =\t(mem_select == MEM_SEL_%d) ? i_m_adr - MEM_OFFSET_%d: 32'h0;\n" % (
                i, i, i)
        assign_buf += "assign o_s%d_dat  =\t(mem_select == MEM_SEL_%d) ? i_m_dat: 32'h0;\n" % (
            i, i)
        assign_buf += "\n"

    #data in block
    data_block_buf = "//data in from slave\n"
    data_block_buf += "always @ (mem_select"
    for i in range(0, num_mems):
        data_block_buf += " or i_s%d_dat" % i

    data_block_buf += ") begin\n\tcase (mem_select)\n"
    for i in range(0, num_mems):
        data_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_dat <= i_s%d_dat;\n\t\tend\n" % (
            i, i)
    data_block_buf += "\t\tdefault: begin\n\t\t\to_m_dat <= 32\'h0000;\n\t\tend\n\tendcase\nend\n\n"

    #ack in block
    ack_block_buf = "//ack in from mem slave\n"
    ack_block_buf += "always @ (mem_select"
    for i in range(0, num_mems):
        ack_block_buf += " or i_s%d_ack" % i
    ack_block_buf += ") begin\n\tcase (mem_select)\n"
    for i in range(0, num_mems):
        ack_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_ack <= i_s%d_ack;\n\t\tend\n" % (
            i, i)
    ack_block_buf += "\t\tdefault: begin\n\t\t\to_m_ack <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"

    #int in block
    int_block_buf = "//int in from slave\n"
    int_block_buf += "always @ (mem_select"
    for i in range(0, num_mems):
        int_block_buf += " or i_s%d_int" % (i)
    int_block_buf += ") begin\n\tcase (mem_select)\n"
    for i in range(0, num_mems):
        int_block_buf += "\t\tMEM_SEL_%d: begin\n\t\t\to_m_int <= i_s%d_int;\n\t\tend\n" % (
            i, i)
    int_block_buf += "\t\tdefault: begin\n\t\t\to_m_int <= 1\'h0;\n\t\tend\n\tendcase\nend\n\n"

    buf = template.substitute(PORTS=port_buf,
                              MEM_SELECT=mem_select_buf,
                              ASSIGN=assign_buf,
                              DATA=data_block_buf,
                              ACK=ack_block_buf,
                              INT=int_block_buf,
                              MEM_PARAMS=param_buf)
    buf = string.expandtabs(buf, 2)

    return buf
    def initialize_graph(self, debug=False):
        """Initializes the graph and project tags."""
        # Clear any previous data.
        #print "initialize graph"
        self.gm.clear_graph()

        # Set the bus type.
        if self.config_dict["TEMPLATE"] == "wishbone_template.json":
            self.set_bus_type("wishbone")
        elif self.config_dict["TEMPLATE"] == "axi_template.json":
            self.set_bus_type("axi")
        else:
            raise WishboneModelError("Template is not specified")

        if "constraint_files" not in self.config_dict:
            self.config_dict["constraint_files"] = []

        if "board" in self.config_dict:
            if len(self.config_dict["constraint_files"]) == 0:
                cfiles = utils.get_constraint_filenames(self.config_dict["board"])
                for cf in cfiles:
                    self.config_dict["constraint_files"].append(cf)

        # Add the nodes that are always present.
        self.gm.add_node("Host Interface", NodeType.HOST_INTERFACE)
        self.gm.add_node("Master", NodeType.MASTER)
        self.gm.add_node("Memory", NodeType.MEMORY_INTERCONNECT)
        self.gm.add_node("Peripherals", NodeType.PERIPHERAL_INTERCONNECT)
        self.add_slave("SDB", SlaveType.PERIPHERAL, slave_index=0)

        # Attach all the appropriate nodes.
        self.gm.connect_nodes(HOST_INTERFACE, MASTER)
        self.gm.connect_nodes(MASTER, MEMORY_BUS)
        self.gm.connect_nodes(MASTER, PERIPHERAL_BUS)
        self.gm.connect_nodes(PERIPHERAL_BUS, SDB)

        # Get module data for the SDB
        # Attempt to load data from the tags.
        #print "Config Dict: %s" % str(self.config_dict)
        if "SLAVES" in self.config_dict:
            for slave_name in self.config_dict["SLAVES"]:
                if slave_name == "SDB":
                    continue
                #Get the slave tags for this project
                slave_project_tags = self.config_dict["SLAVES"][slave_name]
                module_tags = {}
                #Check to see if there is a file for this slave
                if "filename" in slave_project_tags:
                    filename = slave_project_tags["filename"]
                    try:
                        filepath = utils.find_rtl_file_location(filename, self.paths)
                        module_tags = vutils.get_module_tags(filepath)
                    except IOError as ex:
                        #File not found, there is no associated tags with this
                        print "File: %s not found, passing in an empty module" % filename

                uname = self.add_slave(slave_name,
                                       SlaveType.PERIPHERAL,
                                       module_tags = module_tags,
                                       slave_project_tags = slave_project_tags)

        # Load all the memory slaves.
        if "MEMORY" in self.config_dict:
            for slave_name in self.config_dict["MEMORY"]:
                #Get the slave tags for thir project
                slave_project_tags = self.config_dict["MEMORY"][slave_name]
                module_tags = {}
                #Check to see if there is a file for this slave
                if "filename" in slave_project_tags:
                    filename = slave_project_tags["filename"]
                    try:
                        filepath = utils.find_rtl_file_location(filename, self.paths)
                        module_tags = vutils.get_module_tags(filepath)
                    except IOError as ex:
                        #File not found, there is no verilog core associated with this slave on this machine
                        print "File: %s not found, no verilog core associated with this module" % filename

                uname = self.add_slave(slave_name,
                                        SlaveType.MEMORY,
                                        module_tags = module_tags,
                                        slave_project_tags = slave_project_tags)


        #Now that all the slaves are connected I need to connect any arbiters
        if "SLAVES" in self.config_dict:
            for slave_name in self.config_dict["SLAVES"]:
                #print "working on slave: %s" % slave_name
                slave_project_tags = self.config_dict["SLAVES"][slave_name]

                if "BUS" not in slave_project_tags:
                    continue

                #bus_dict = copy.deepcopy(slave_project_tags["BUS"])
                from_slave_uname = self.get_unique_from_module_name(slave_name)
                for arbiter in slave_project_tags["BUS"]:
                    slave_module_name = slave_project_tags["BUS"][arbiter]
                    #print "slave_module_name: %s" % slave_module_name
                    try:
                        to_slave_uname = self.get_unique_from_module_name(slave_module_name)
                    except gm.SlaveError as ex:
                        to_slave_uname = slave_module_name
                    slave_project_tags["BUS"][arbiter] = to_slave_uname
                    self.connect_arbiter(from_slave_uname, arbiter, to_slave_uname)


        # Check if there is a host interface defined.
        if "INTERFACE" in self.config_dict:
            self.setup_host_interface()

        if debug:
            print ("Finish Initialize graph")
Exemple #11
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    def gen_som(self, tags={}, buf="", user_paths=[], debug=False):
        tags = copy.deepcopy(tags)
        self.rom_element_count = 0
        if "MEMORY" not in tags:
            tags["MEMORY"] = {}

        self.user_paths = user_paths
        board_name = tags["board"].lower()

        if not utils.board_exists(board_name):
            try:
                utils.install_remote_board_package(board_name)
            except IBuilderError as e:
                raise IBuilderError(                                            \
                                "Board %s could not be found, Attempted to "    \
                                "find it in the remote table and failed. If "   \
                                "this is a local board make sure to run the "   \
                                "local install" % (board_name))

        image_id = 0
        for key in tags.keys():
            if key.lower() == "image_id":
                image_id = tags[key]

        sm = som.SOM()
        sm.initialize_root()
        root = sm.get_root()
        #Add 1 for Root
        self.rom_element_count += 1

        peripheral = sm.insert_bus(root, name="peripheral")
        memory = sm.insert_bus(root, name="memory")

        #Add one for SDB ROM
        self.rom_element_count += 1
        self.rom_element_count += 1
        version_major = device_manager.get_device_id_from_name("SDB")
        sdb_rom = sdbc.create_device_record(name="SDB",
                                            version_major=version_major)

        #Add two for bridge and one extra for empty
        self.rom_element_count += 3

        #Peripheral Bus
        #Add one for interconnect
        self.rom_element_count += 1
        '''
        #Move all the platform peripherals to the front of the SDB Bus
        temp_unordered_platform_tags = {}
        temp_platform_tags = OrderedDict()
        temp_periph_tags = OrderedDict()
        minor_dict = {}
        peripheral_id = device_manager.get_device_id_from_name("platform")

        for key in tags["SLAVES"]:
            filename = tags["SLAVES"][key]["filename"]
            absfilename = utils.find_rtl_file_location(filename, self.user_paths)
            f = open(absfilename, 'r')
            slave_buffer = f.read()
            f.close()

            per = sdbc.create_device_record(name = key)
            per.parse_buffer(slave_buffer)

            if per.get_abi_version_major_as_int() == peripheral_id:
                minor = per.get_abi_version_minor_as_int()
                minor_dict[minor] = key
                temp_unordered_platform_tags[key] = tags["SLAVES"][key]
            else:
                temp_periph_tags[key] = tags["SLAVES"][key]

        if len(minor_dict.keys()) > 0:
            #Order the platforms in terms of their minor numbers
            ordered_keys = sorted(minor_dict.keys(), key=int)
            for okey in ordered_keys:
                key = minor_dict[okey]
                temp_platform_tags[key] = temp_unordered_platform_tags[key]
            
            #Add all the peripheral slaves
            for key in temp_periph_tags:
                temp_platform_tags[key] = temp_periph_tags[key]
            
            #Put the slaves back in the original dictionary
            tags["SLAVES"] = temp_platform_tags
        '''

        #Add one per peripheral
        for i in range(0, len(tags["SLAVES"])):
            key = tags["SLAVES"].keys()[i]

            if is_integration_required(tags["SLAVES"][key]):
                ir = generate_integration_record(tags["SLAVES"], key)
                #print "Inserting Integration record for: %s" % key
                sm.insert_component(peripheral, ir)

            filename = tags["SLAVES"][key]["filename"]
            absfilename = utils.find_rtl_file_location(filename,
                                                       self.user_paths)
            f = open(absfilename, 'r')
            slave_buffer = f.read()
            f.close()

            per = sdbc.create_device_record(name=key)
            per.parse_buffer(slave_buffer)
            per.set_name(str(key))
            sm.insert_component(peripheral, per)
            self.rom_element_count += 1

        #Add one for empty
        self.rom_element_count += 1

        #Memory Bus
        #Add one for interconnect
        self.rom_element_count += 1

        #Add one per memory peripheral
        for i in range(0, len(tags["MEMORY"])):
            key = tags["MEMORY"].keys()[i]
            name = tags["MEMORY"][key]["filename"]
            absfilename = utils.find_rtl_file_location(name, self.user_paths)
            f = open(absfilename, 'r')
            memory_buffer = f.read()
            f.close()

            mem = sdbc.create_device_record(name=key)
            mem.parse_buffer(memory_buffer)
            mem.set_name(str(key))
            sm.insert_component(memory, mem)
            self.rom_element_count += 1

        #add one for empty
        self.rom_element_count += 1

        #TODO: add Add one for URL of repo ?? Maybe
        #TODO: add Add one for Synthesis Record
        self.rom_element_count += 1

        sdb_rom.set_size(self.rom_element_count * sdbc.SDB_ROM_RECORD_LENGTH)
        sm.insert_component(peripheral, sdb_rom, 0)

        #Generate the ROM image
        sm.set_child_spacing(root, 0x0100000000)
        sm.set_child_spacing(peripheral, 0x0001000000)
        return sm